Circuit operation verification method and apparatus

1. A computer-readable, non-transitory storage medium storing a circuit operation verification program for causing a computer to execute a process, comprising: based on logic simulation results for an operation verification target circuit including a control circuit instructing a switching restraining mode to a specific circuit, identifying, from a control signal data storage device storing an ID of a control signal net through which a control signal to instruct said switching restraining mode is transmitted, a signal value of said control signal, by which said switching restraining mode is enabled, and an ID of a switching restrained net, through which a signal directly influenced by enabling said switching restraining mode is transmitted, in association each other, a switching restrained net, for which said signal value of said control signal of said control signal net at a specific time is a signal value by which said switching restraining mode is enabled, and which corresponds to the pertinent control signal net, and setting a switching probability restraint information list including said ID of the identified switching restrained net and said specific time to said identified switching restrained net; identifying, from a propagation condition data storage device storing, for each type of the circuit, a propagation condition by which said switching probability restraint information list set for an input side net of the circuit is propagated to an output side net of the circuit, a propagation condition for a type of a specific circuit whose input side net is a net for which said switching probability restraint information list is set, and judging whether or not said results of logic simulation satisfy the identified propagation condition, and propagating said switching probability restraint information list set for said input side net to said output side net of said specific circuit, upon detecting that said results of said logic simulation satisfy said identified propagation condition; and judging whether or not said specific time included in said switching probability restraint information list propagated to said output side net of said specific circuit is a time prior to a predetermined time or more from a present time, and upon detecting that said specific time is a time prior to said predetermined time or more from said present time, outputting an error.

2. The computer-readable, non-transitory storage medium as set forth in claim 1 , wherein said process further comprises: comparing data of said operation verification target circuit with data of a circuit before said control circuit is added, to identify difference circuits, and comparing, by using said difference circuits, said data of said operation verification target circuit with switching restraint circuit patterns each having a control circuit, a controlled circuit, a control signal net of an input side, which connects said control circuit with said controlled circuit and transmits said control signal, and a switching restrained net of an output side of said controlled circuit, wherein said switching restraint circuit patterns are stored in a control signal detection library storage device further storing a signal value of said control signal, by which said switching restraining mode is enabled for said switching restraint circuit pattern; and identifying said control signal net, said signal value of said control signal and said switching restraint net for a circuit pattern pertinent to said switching restraint circuit pattern in said data of said operation verification target circuit, and storing the identified data into said control signal data storage device.

3. The computer-readable, non-transitory storage medium as set forth in claim 1 , wherein said process comprises: counting a number of times that at least one of said setting said switching probability restraint information list and said propagating said switching probability restraint information list is carried out, and storing the count value into a switching restraint count value storage device in association with said ID of said control signal net.

4. The computer-readable, non-transitory storage medium as set forth in claim 1 , wherein said process comprises: counting a number of times that transition of said signal value in said results of said logic simulation is observed, for a net for which different switching probability restraint information lists are consecutively set, and storing the count value into a signal change count value storage device in association with the pertinent net.

5. The computer-readable, non-transitory storage medium as set forth in claim 1 , wherein said identifying and setting comprises deleting said switching probability restraint information list already set for an output side, at beginning of a processing for a specific time.

6. A computer-implemented circuit operation verification method, comprising: based on logic simulation results for an operation verification target circuit including a control circuit instructing a switching restraining mode to a specific circuit, identifying, by using a computer, from a control signal data storage device storing an ID of a control signal net through which a control signal to instruct said switching restraining mode is transmitted, a signal value of said control signal, by which said switching restraining mode is enabled, and an ID of a switching restrained net, through which a signal directly influenced by enabling said switching restraining mode is transmitted, in association with each other, a switching restrained net, for which said signal value of said control signal of said control signal net at a specific time is a signal value by which said switching restraining mode is enabled, and which corresponds to the pertinent control signal net, and setting a switching probability restraint information list including said ID of the identified switching restrained net and said specific time to said identified switching restrained net; identifying, by using the computer, from a propagation condition data storage device storing, for each type of the circuit, a propagation condition by which said switching probability restraint information list set for an input side net of the circuit is propagated to an output side net of the circuit, a propagation condition for a type of a specific circuit whose input side net is a net for which said switching probability restraint information list is set, and judging whether or not said results of logic simulation satisfy the identified propagation condition, and propagating said switching probability restraint information list set for said input side net to said output side net of said specific circuit, upon detecting that said results of said logic simulation satisfy said identified propagation condition; and judging, by using the computer, whether or not said specific time included in said switching probability restraint information list propagated to said output side net of said specific circuit is a time prior to a predetermined time or more from a present time, and upon detecting that said specific time is a time prior to said predetermined time or more from said present time, outputting an error.

7. A circuit operation verification apparatus, comprising: a control signal data storage device storing an ID of a control signal net through which a control signal to instruct said switching restraining mode is transmitted, a signal value of said control signal, by which said switching restraining mode is enabled, and an ID of a switching restrained net, through which a signal directly influenced by enabling said switching restraining mode is transmitted, in association each other; a setting unit that identifies, based on logic simulation results for an operation verification target circuit including a control circuit instructing a switching restraining mode to a specific circuit, a switching restrained net, for which said signal value of said control signal of said control signal net at a specific time is a signal value by which said switching restraining mode is enabled, and which corresponds to the pertinent control signal net, from said control signal data storage device, and sets a switching probability restraint information list including said ID of the identified switching restrained net and said specific time to said identified switching restrained net; a propagation condition data storage device storing, for each type of the circuit, a propagation condition by which said switching probability restraint information list set for an input side net of the circuit is propagated to an output side net of the circuit; a propagation unit that identifies, from said propagation condition data storage device, a propagation condition for a type of a specific circuit whose input side net is a net for which said switching probability restraint information list is set, and judges whether or not said results of logic simulation satisfy the identified propagation condition, and propagates said switching probability restraint information list set for said input side net to said output side net of said specific circuit, upon detecting that said results of said logic simulation satisfy said identified propagation condition; and an output unit that judges whether or not said specific time included in said switching probability restraint information list propagated to said output side net of said specific circuit is a time prior to a predetermined time or more from a present time, and upon detecting that said specific time is a time prior to said predetermined time or more from said present time, outputs an error.