Component built-in wiring substrate and manufacturing method thereof

1. A component built-in wiring substrate comprising: a core substrate, which is formed of a resin, including a core principal surface, a core rear surface, and a housing hole portion having an opening on the core principal surface side; a plate-shaped component, which is formed of a ceramic material, that has a component principal surface and a component rear surface and is housed in the housing hole portion in a state in which the core principal surface and the component principal surface are disposed to face a same side; a resin filling portion that is filled in a gap between an inner wall face of the housing hole portion and the plate-shaped component and that fixes the plate-shaped component to the core substrate; and a wiring stacking portion that is formed by alternately stacking resin interlayer insulating layers and a conductive layer on the core principal surface and the component principal surface and that has a plurality of solder bumps disposed inside a mounting area for mounting a chip component configured on the uppermost layer, wherein, when viewed from the core principal surface side, the projected area of the mounting area is larger than the projected area of the plate-shaped component and the resin filling portion, and the plate-shaped component and the resin filling portion are positioned directly below the mounting area, and wherein a value of the coefficient of thermal expansion (CTE α 2 ) for a temperature range that is equal to or higher than the glass transition temperature of the resin filling portion is set to be larger than a value of the coefficient of thermal expansion of the plate-shaped component for said temperature range and is set to be smaller than the value of the coefficient of thermal expansion of the core substrate for said temperature range.

2. The component built-in wiring substrate according to claim 1 , wherein the absolute value of a difference between the value of the coefficient of thermal expansion (CTE α 2 ) of the resin filling portion for the temperature range that is equal to or higher than the glass transition temperature and a value of the coefficient of thermal expansion (CTE α 1 ) of the resin filling portion for a temperature range that is lower than the glass transition temperature is equal to or smaller than 50 ppm/° C.

3. The component built-in wiring substrate according to claim 2 , wherein the value of the coefficient of thermal expansion (CTE α 2 ) of the resin filling portion for the temperature range that is equal to or higher than the glass transition temperature is equal to or smaller than 90 ppm/° C.

4. The component built-in wiring substrate according to claim 3 , wherein the value of the coefficient of thermal expansion (CTE α 2 ) of the resin filling portion for the temperature range that is equal to or higher than the glass transition temperature is equal to or smaller than 60 ppm/° C.

5. The component built-in wiring substrate according to claim 1 , wherein the Young's modulus of the resin filling portion is equal to or larger than 6.0 GPa.

6. The component built-in wiring substrate according to claim 1 , wherein the coefficient of extension of the resin filling portion is equal to or smaller than 3.5%.

7. The component built-in wiring substrate according to claim 1 , wherein the resin of the resin filling portion contains an inorganic filler, and wherein the content of the inorganic filler is equal to or larger than 50 wt % based on the weight of the inorganic filler and the resin.

8. The component built-in wiring substrate according to claim 1 , wherein the plate-shaped component is a ceramic capacitor.

9. The component built-in wiring substrate according to claim 1 , wherein the plate-shaped component has a structure in which a plurality of internal electrode layers are disposed so as to be stacked through a ceramic dielectric layer and includes a plurality of in-capacitor via conductors, which in-capacitor conductors are connected to respective ones of the plurality of internal electrode layers, and a plurality of surface layer electrodes connected to at least end portions of the plurality of respective ones of the in-capacitor via conductors that are located on the component principal surface side, and wherein the plurality of in-capacitor via conductors are arranged in an array so as to define a ceramic capacitor.

10. A component built-in wiring substrate comprising: a core substrate, which is formed of a resin, including a core principal surface, a core rear surface, and a housing hole portion having an opening on the core principal surface side; a plate-shaped component, which is formed of a ceramic material, that has a component principal surface and a component rear surface and is housed in the housing hole portion in a state in which the core principal surface and the component principal surface are disposed to face a same side; a resin filling portion that is filled in a gap between an inner wall face of the housing hole portion and the plate-shaped component and that fixes the plate-shaped component to the core substrate; and a wiring stacking portion that is formed by alternately stacking resin interlayer insulating layers and a conductive layer on the core principal surface and the component principal surface and that has a plurality of solder bumps disposed inside a mounting area for mounting a chip component configured on the uppermost layer, wherein, when viewed from the core principal surface side, the projected area of the mounting area is larger than the projected area of the plate-shaped component and the resin filling portion, and the plate-shaped component and the resin filling portion are positioned directly below the mounting area, and wherein a value of the coefficient of thermal expansion (CTE α 2 ) for a temperature range that is equal to or higher than the glass transition temperature of the resin filling portion is set to be larger than a value that is acquired by decreasing a value of the coefficient of thermal expansion of the plate-shaped component for said temperature range by 10% and is set to be smaller than a value that is acquired by increasing a value of the coefficient of thermal expansion of the core substrate for said temperature range by 10%.

11. A component built-in wiring substrate comprising: a core substrate, which is formed of a resin, including a core principal surface, a core rear surface, and a housing hole portion having an opening on the core principal surface side; a plate-shaped component, which is formed of a ceramic material, that has a component principal surface and a component rear surface and is housed in the housing hole portion in a state in which the core principal surface and the component principal surface are disposed to face a same side; a resin filling portion that is filled in a gap between an inner wall face of the housing hole portion and the plate-shaped component and that fixes the plate-shaped component to the core substrate; and a wiring stacking portion that is formed by alternately stacking resin interlayer insulating layers and a conductive layer on the core principal surface and the component principal surface and that has a plurality of solder bumps disposed inside a mounting area for mounting a chip component configured on the uppermost layer, wherein, when viewed from the core principal surface side, the projected area of the mounting area is larger than the projected area of the plate-shaped component and the resin filling portion, and the plate-shaped component and the resin filling portion are positioned directly below the mounting area, and wherein a value of the coefficient of thermal expansion (CTE α 1 ) for a temperature range that is lower than the glass transition temperature of the resin filling portion is set to be larger than a value of the coefficient of thermal expansion of the plate-shaped component for said temperature range and is set to be smaller than the value of the coefficient of thermal expansion of the core substrate for said temperature range.

12. The component built-in wiring substrate according to claim 11 , wherein the absolute value of a difference between the value of the coefficient of thermal expansion (CTE α 2 ) of the resin filling portion for the temperature range that is equal to or higher than the glass transition temperature and a value of the coefficient of thermal expansion (CTE α 1 ) of the resin filling portion for a temperature range that is lower than the glass transition temperature is equal to or smaller than 50 ppm/° C.

13. The component built-in wiring substrate according to claim 12 , wherein the value of the coefficient of thermal expansion (CTE α 2 ) of the resin filling portion for the temperature range that is equal to or higher than the glass transition temperature is equal to or smaller than 90 ppm/° C.

14. The component built-in wiring substrate according to claim 13 , wherein the value of the coefficient of thermal expansion (CTE α 2 ) of the resin filling portion for the temperature range that is equal to or higher than the glass transition temperature is equal to or smaller than 60 ppm/° C.

15. The component built-in wiring substrate according to claim 11 , wherein the Young's modulus of the resin filling portion is equal to or larger than 6.0 GPa.

16. The component built-in wiring substrate according to claim 11 , wherein the coefficient of extension of the resin filling portion is equal to or smaller than 3.5%.

17. The component built-in wiring substrate according to claim 11 , wherein the resin of the resin filling portion contains an inorganic filler, and wherein the content of the inorganic filler is equal to or larger than 50 wt % based on the weight of the inorganic filler and the resin.

18. The component built-in wiring substrate according to claim 11 , wherein the plate-shaped component is a ceramic capacitor.

19. The component built-in wiring substrate according to claim 11 , wherein the plate-shaped component has a structure in which a plurality of internal electrode layers are disposed so as to be stacked through a ceramic dielectric layer and includes a plurality of in-capacitor via conductors, which in-capacitor conductors are connected to respective ones of the plurality of internal electrode layers, and a plurality of surface layer electrodes connected to at least end portions of the plurality of respective ones of the in-capacitor via conductors that are located on the component principal surface side, and wherein the plurality of in-capacitor via conductors are arranged in an array so as to define a ceramic capacitor.

20. A component built-in wiring substrate comprising: a core substrate, which is formed of a resin, including a core principal surface, a core rear surface, and a housing hole portion having an opening on the core principal surface side; a plate-shaped component, which is formed of a ceramic material, that has a component principal surface and a component rear surface and is housed in the housing hole portion in a state in which the core principal surface and the component principal surface are disposed to face a same side; a resin filling portion that is filled in a gap between an inner wall face of the housing hole portion and the plate-shaped component and that fixes the plate-shaped component to the core substrate; and a wiring stacking portion that is formed by alternately stacking resin interlayer insulating layers and a conductive layer on the core principal surface and the component principal surface and that has a plurality of solder bumps disposed inside a mounting area for mounting a chip component configured on the uppermost layer, wherein, when viewed from the core principal surface side, the projected area of the mounting area is larger than the projected area of the plate-shaped component and the resin filling portion, and the plate-shaped component and the resin filling portion are positioned directly below the mounting area, and wherein a value of the coefficient of thermal expansion (CTE α 1 ) for a temperature range that is lower than the glass transition temperature of the resin filling portion is set to be larger than a value that is acquired by decreasing a value of the coefficient of thermal expansion of the plate-shaped component for said temperature range by 10% and is set to be smaller than a value that is acquired by increasing the value of the coefficient of thermal expansion of the core substrate for said temperature range by 10%.