A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a graphene layer including at least one graphene monolayer, said method comprising: forming a semiconductor-carbon alloy layer comprising a material other than crystalline silicon carbide on a semiconductor substrate; converting said semiconductor-carbon alloy layer into a semiconductor carbide layer by a first anneal; and converting an exposed top portion of said semiconductor carbide layer into a graphene layer including at least one graphene monolayer by a second anneal.
2. The method of claim 1 , wherein said semiconductor substrate is a single crystalline silicon-containing-semiconductor substrate.
3. The method of claim 1 , wherein said semiconductor-carbon alloy layer is formed on at least one of a single-crystalline semiconductor surface of said semiconductor substrate, a dielectric surface located on a top surface of said semiconductor substrate, a semiconductor mesa structure protruding on a top surface of said semiconductor substrate, a recessed semiconductor surface that is recessed from a top surface of said semiconductor substrate, and a top semiconductor layer of an extremely thin semiconductor-on-insulator (ETSOI) structure wherein said top semiconductor layer has a thickness less than 5 nm.
4. The method of claim 1 , wherein said semiconductor-carbon alloy layer is a layer of a silicon-carbon alloy, wherein carbon has an atomic concentration from 20% to 75% in said silicon-carbon alloy, and wherein said semiconductor carbide layer is a silicon carbide (SiC) layer.
5. The method of claim 1 , wherein said semiconductor-carbon alloy layer is a layer of a silicon-germanium-carbon alloy, wherein carbon has an atomic concentration from 20% to 75% in said silicon-germanium-carbon alloy, wherein said semiconductor carbide layer is a silicon-germanium carbide (Si x Ge 1-x C) layer, and wherein x is from 0 to 1.
6. The method of claim 1 , wherein said semiconductor-carbon alloy layer is a layer of a germanium-carbon alloy, wherein carbon has an atomic concentration from 20% to 75% in said germanium-carbon alloy, and wherein said semiconductor carbide layer is a germanium carbide (GeC) layer.
7. The method of claim 1 , wherein said semiconductor-carbon alloy layer is a superlattice including multiple repetitions of a first material layer and a second material layer, wherein at least one of said first material layer and a second material layer includes carbon and at least one of said first material layer and a second material layer includes at least one of silicon and germanium.
8. The method of claim 7 , wherein said first material layer includes silicon, germanium, or an alloy of silicon and said second material layer may include carbon or a carbon alloy.
9. The method of claim 1 , wherein said semiconductor-carbon alloy layer is deposited by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or vacuum evaporation at a temperature from 400° C. to 1,000° C.
10. The method of claim 9 , wherein said semiconductor-carbon alloy layer is amorphous as deposited and prior to said first anneal.
11. The method of claim 9 , wherein said first anneal is performed at a temperature greater than a deposition temperature of said semiconductor-carbon alloy layer, and wherein said first anneal is effected by at least one of a furnace anneal at a uniform temperature, a scanned laser anneal, a furnace anneal in which a non-uniform temperature gradient is provided across said semiconductor substrate wherein a local maximum temperature region on said semiconductor substrate moves continuously from one side of said semiconductor substrate to an opposite side of said semiconductor substrate.
12. The method of claim 1 , wherein said second anneal is performed at a temperature greater than 1,200° C., and wherein semiconductor atoms other than carbon atoms in said semiconductor carbide layer are evaporated from said exposed top portion of said semiconductor carbide layer, wherein remaining carbon atoms coalesce into said graphene layer.
13. The method of claim 1 , further comprising structurally damaging said exposed top portion of said semiconductor-carbon alloy layer by at least one of low energy ion implantation, plasma treatment, gas cluster ion beam treatment, and a reactive ion etch, wherein movement of carbon atoms to said exposed top portion is accelerated by damage gettering of carbon.
14. The method of claim 1 , further comprising: forming a metal capping layer directly on said semiconductor-carbon alloy layer; performing a third anneal at a temperature from 300° C. to 600° C., wherein carbon atoms are segregated within said semiconductor-carbon alloy layer toward an interface between said metal capping layer and said semiconductor-carbon alloy layer; and removing said metal capping layer selective to said semiconductor-carbon alloy layer prior to said first anneal.
15. A method of forming a graphene layer including at least one graphene monolayer, said method comprising: providing a semiconductor substrate having at least one semiconductor surface and at least one dielectric surface on a top side; forming a semiconductor-carbon alloy layer selectively on said at least one semiconductor surface, wherein nucleation and growth of a semiconductor-carbon alloy material is suppressed on said at least one dielectric surface; converting said semiconductor-carbon alloy layer into a semiconductor carbide layer by a first anneal; and converting an exposed top portion of said semiconductor carbide layer into a graphene layer including at least one graphene monolayer by a second anneal, wherein said at least one dielectric surface remains exposed.
16. The method of claim 15 , wherein said semiconductor-carbon alloy layer is formed on at least one of a single-crystalline semiconductor surface of said semiconductor substrate, a semiconductor mesa structure protruding on a top surface of said semiconductor substrate, a recessed semiconductor surface that is recessed from a top surface of said semiconductor substrate, and a top semiconductor layer of an extremely thin semiconductor-on-insulator (ETSOI) structure wherein said top semiconductor layer has a thickness less than 5 nm, and wherein said semiconductor-carbon alloy layer does not grow from said dielectric surface.
17. The method of claim 15 , wherein said semiconductor-carbon alloy layer is deposited by chemical vapor deposition (CVD) at a temperature from 400° C. to 1,000° C., and wherein a first source gas for a semiconductor material, a second source gas for carbon, and an etchant gas are flowed into a reactor concurrently or sequentially.
18. The method of claim 15 , wherein said second anneal is performed at a temperature greater than 1,200° C., and wherein semiconductor atoms other than carbon atoms in said semiconductor carbide layer are evaporated from said exposed top portion of said semiconductor carbide layer, wherein remaining carbon atoms coalesce into said graphene layer.
19. The method of claim 15 , further comprising structurally damaging said exposed top portion of said semiconductor carbide layer by at least one of low energy ion implantation, a plasma treatment, a gas cluster ion beam treatment, and a reactive ion etch, wherein movement of carbon atoms to said exposed top portion is accelerated by damage gettering of carbon.
20. A method of forming a graphene layer including at least one graphene monolayer, said method comprising: forming a semiconductor-carbon alloy layer on a semiconductor substrate; converting said semiconductor-carbon alloy layer into a semiconductor carbide layer by a a first anneal; and converting an exposed top portion of said semiconductor carbide layer into a graphene layer including at least one graphene monolayer by a second anneal, wherein said semiconductor-carbon alloy layer is formed on at least one of a single-crystalline semiconductor surface of said semiconductor substrate, a dielectric surface located on a top surface of said semiconductor substrate, a semiconductor mesa structure protruding on a top surface of said semiconductor substrate, a recessed semiconductor surface that is recessed from a top surface of said semiconductor substrate, and a top semiconductor layer of an extremely thin semiconductor-on-insulator (ETSOI) structure wherein said top semiconductor layer has a thickness less than 5 nm.
21. A method of forming a graphene layer including at least one graphene monolayer, said method comprising: forming a semiconductor-carbon alloy layer on a semiconductor substrate; converting said semiconductor-carbon alloy layer into a semiconductor carbide layer by a a first anneal; and converting an exposed top portion of said semiconductor carbide layer into a graphene layer including at least one graphene monolayer by a second anneal, wherein said semiconductor-carbon alloy layer is a superlattice including multiple repetitions of a first material layer and a second material layer, wherein at least one of said first material layer and a second material layer includes carbon and at least one of said first material layer and a second material layer includes at least one of silicon and germanium.
22. The method of claim 21 , wherein said first material layer includes silicon, germanium, or an alloy of silicon and said second material layer may include carbon or a carbon alloy.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 24, 2009
May 29, 2012
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