A memory controller may execute instructions instead of sending the instructions to a processor for execution. To maintain synchronization between the memory controller and the processor, the memory controller may queue a null instruction in the memory controller for each non-filler instruction sent to the processor and may send a filler instruction to the processor for each non-null instruction to be executed by the memory controller.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of a memory controller to interface a processor to a memory comprising: fetching an instruction from the memory; and sending a filler instruction to the processor for the fetched instruction to be executed by the memory controller in response to a determination that the fetched instruction is to be executed by the memory controller based on a comparison of an opcode of the fetched instruction with stored information that indicates which opcodes are to cause a corresponding instruction to be executed by the memory controller, wherein the fetched instruction is to be executed by the memory controller and the filler instruction is to be executed by the processor.
2. The method of claim 1 , further comprising fetching another instruction from the memory, determining the another instruction is to be executed by the processor, sending the another instruction to the processor for execution by the processor, and queuing a null instruction in the memory controller that corresponds to the another instruction sent to the processor.
3. The method of claim 1 , further comprising queuing the instruction until executed by the memory controller.
4. The method of claim 1 , further comprising queuing the instruction until executed by the memory controller, and flushing any queued instructions in response to a pipeline flush signal from the processor.
5. The method of claim 1 , further comprising queuing a null instruction in the memory controller that corresponds to the another instruction sent to the processor for execution, and halting execution of queued instructions to be executed by the memory controller in response to the memory controller executing the null instruction.
6. The method of claim 1 , further comprising queuing a null instruction in the memory controller that corresponds to the another instruction sent to the processor for execution, halting execution of queued instructions to be executed by the memory controller in response to the memory controller executing the null instruction, and resuming execution of the queued instructions in response to a dequeue signal from the processor.
7. The method of claim 1 , further comprising queuing a null instruction in the memory controller that corresponds to the another instruction sent to the processor for execution, halting execution of queued instructions to be executed by the memory controller in response to the memory controller executing the null instruction, and dequeuing a plurality of consecutive null instructions that comprises the null instruction that resulted in halting execution in response to a dequeue signal from the processor.
8. The method of claim 1 , wherein executing the instruction comprises executing the instruction in response to a dequeue signal from the processor.
9. The method of claim 1 , wherein for each instruction in a pipeline of the memory controller, a corresponding filler instruction is to be stored in a pipeline of the processor.
10. The method of claim 1 , further comprising the processor asserting a dequeue signal for a pipeline of the memory controller only once for a plurality of contiguous filler instructions stored in a pipeline of the processor.
11. For use with a memory controller that provides an interface to a memory, a method of a processor comprising: queuing instructions received from the memory controller, executing queued instructions, and requesting the memory controller to resume execution of instructions queued in the memory controller in response to executing a filler instruction by the processor, wherein the filler instruction is to be queued in response to a determination that an instruction is to be executed by the memory controller based on a comparison of an opcode of the instruction with stored information that indicates which opcodes are to cause a corresponding instruction to be executed by the memory controller, wherein the instruction is to be executed by the memory controller and the filler instruction is to be executed by the processor.
12. The method of claim 11 wherein requesting comprises asserting a dequeue signal to request the memory controller to resume execution of instructions queued in the memory controller.
13. The method of claim 11 , further comprising flushing the queued instructions from the processor, and requesting the memory controller to flush instructions to be executed by the memory controller.
14. The method of claim 11 , further comprising flushing the queued instructions from the processor, and asserting a flush signal to inform the memory controller that the processor flushed the queued instructions.
15. The method of claim 11 , further comprising dequeuing a plurality of consecutive filler instructions that comprises the filler instruction that resulted in requesting the memory controller to resume execution.
16. The method of claim 11 , further comprising determining the memory controller has completed execution of instructions associated with a previous request to resume execution prior to requesting the memory controller to resume execution.
17. A memory controller comprising: a pipeline to queue instructions, an execution logic to execute instructions of the pipeline, an instruction interpretation unit to send a filler instruction to a processor in response to a determination that an instruction fetched from a memory is to be executed by the memory controller based on a comparison of an opcode of the fetched instruction with stored information that indicates which opcodes are to cause a corresponding instruction to be executed by the memory controller, wherein the fetched instruction is to be executed by the memory controller and the filler instruction is to be executed by the processor.
18. The memory controller of claim 17 , wherein the instruction interpretation unit stores another instruction fetched from the memory in the pipeline in response to determining that the another instruction is to be executed by the execution logic of the memory controller, and sends a filler instruction to the processor that corresponds to the another instruction queued in the pipeline.
19. The memory controller of claim 17 , wherein the instruction interpretation unit flushes instructions from the pipeline in response to a pipeline flush signal from the processor.
20. The memory controller of claim 17 , wherein the execution logic halts execution of instructions queued in the pipeline in response to executing a null instruction.
21. The memory controller of claim 17 , wherein the execution logic halts execution of instructions queued in the pipeline in response to executing a null instruction, and resumes execution of instructions queued in the pipeline in response to a dequeue signal from the processor.
22. The memory controller of claim 17 , wherein the execution logic halts execution of instructions queued in the pipeline in response to executing a null instruction, and in response to a dequeue signal from the processor, dequeues from the pipeline a plurality of consecutive null instructions that comprises the null instruction that resulted in halting execution.
23. A processor comprising; a pipeline to queue instructions, an execution logic to execute instructions of the pipeline, and to request a memory controller to resume execution of instructions queued in the memory controller in response to executing a filler instruction from the pipeline that is to be provided in response to at least one of the queued instructions and in response to a determination that the at least one queued instruction is to be executed by the memory controller based on a comparison of an opcode of the at least one queued instruction with stored information that indicates which opcodes are to cause a corresponding instruction to be executed by the memory controller, wherein the at least one queued instruction is to be executed by the memory controller and the filler instruction is to be executed by the processor.
24. The processor of claim 23 , wherein the execution logic further requests the memory controller to flush instructions to be executed by the memory controller in response to flushing the pipeline.
25. The processor of claim 23 , wherein the execution logic further dequeues from the pipeline a plurality of consecutive filler instructions that comprises the filler instruction that resulted in requesting the memory controller to resume execution.
26. The processor of claim 23 , wherein the execution logic further determines the memory controller has completed execution of instructions associated with a previous request to resume execution prior to requesting the memory controller to resume execution.
27. A system comprising a memory to store instructions, a processor to execution instructions, and a memory controller to fetch instructions from the memory, to queue instructions for execution by the memory controller, and to send instructions to the processor for execution in response to determining the processor is to execute the instructions, wherein the processor is to request the requests a memory controller to resume execution of instructions queued in the memory controller in response to a determination that the fetched instruction is to be executed by the memory controller based on a comparison of an opcode of the fetched instruction with stored information that indicates which opcodes are to cause a corresponding instruction to be executed by the memory controller, wherein the fetched instruction is to be executed by the memory controller and a filler instruction is to be executed by the processor.
28. The system of claim 27 , further comprising: an execution logic to execute instructions of the pipeline, an instruction interpretation unit to send an instruction fetched from the memory to the processor in response to determining that the instruction is to be executed by the processor, and to store a null instruction in the pipeline in place of each non-filler instruction to be executed by the processor, wherein the memory controller queues a null instruction for each non-filler instruction sent to the processor and sends a filler instruction to the processor for each non-null instruction queued in the memory controller.
29. The system of claim 28 wherein the memory controller halts execution of instructions queued in the memory controller in response to executing a null instruction, and the processor requests the memory controller to resume execution in response to executing a filler instruction.
30. The system of claim 29 wherein the memory controller, in response to a request to resume execution, dequeues from the memory controller a plurality of consecutive null instructions that comprises the null instruction that resulted in halting execution.
31. The system of claim 30 , wherein the processor further dequeues from the pipeline a plurality of consecutive filler instructions that comprises the filler instruction that resulted in requesting the memory controller to resume execution.
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March 10, 2006
May 29, 2012
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