For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of erasing a memory device, comprising: erasing one or more memory cells during an erase operation; determining, internal to the memory device, a number of erase pulses required to erase a sample of the one or more memory cells erased during the erase operation; and adjusting an erase starting voltage level of one or more erase pulses applied to the one or more memory cells during a subsequent erase operation in response, at least in part, to the number of erase pulses required to erase the sample of the one or more memory cells erased during the prior erase operation; wherein the sample of the one or more memory cells erased during the prior erase operation is erased during the subsequent erase operation.
2. The method of claim 1 , wherein adjusting the erase starting voltage level of one or more erase pulses applied to the one or more memory cells during a subsequent erase operation comprises adjusting the erase starting voltage level so that the number of erase pulses applied during the subsequent erase operation will tend toward a target number of erase pulses.
3. The method of claim 2 , wherein the target number is less than the number of erase pulses determined in the prior erase operation.
4. The method of claim 1 , wherein determining a number of erase pulses required to erase the sample of the one or more memory cells erased during the prior erase operation comprises determining an average number of erase pulses it takes to erase the sample of the one or more memory cells erased during the prior erase operation and/or determining the number of erase pulses it takes to erase the sample of the one or more memory cells erased during the prior erase operation a certain number of times after power-up.
5. The method of claim 1 , wherein adjusting an erase starting voltage level of one or more erase pulses applied to the one or more memory cells during a subsequent erase operation is in response to the number of erase pulses required to erase the sample of the one or more memory cells erased during the prior erase operation exceeding a certain number of erase pulses and/or exceeding the certain number of erase pulses by more than one.
6. The method of claim 1 , further comprising storing the number of erase pulses required to erase the sample of the one or more memory cells erased during the prior erase operation.
7. The method of claim 1 , further comprising determining, internal to the memory device, a number of erase pulses required to erase a sample of the one or more memory cells erased during each time an erase operation is performed.
8. A method of erasing a memory device, comprising: determining, internal to the memory device, a number of erase pulses required for erasing a sample of memory cells of the memory device during an erase operation; comparing the determined number of erase pulses required for erasing the sample of memory cells of the memory device to a target number of erase pulses; and adjusting an erase starting voltage level of one or more erase pulses applied to one or more memory cells of the sample of memory cells during a subsequent erase operation when the determined number of erase pulses required for erasing the sample of memory cells in the prior erase operation is different than the target number so that the number of erase pulses applied during the subsequent erase operation tends toward the target number.
9. The method of claim 8 , wherein adjusting the erase starting voltage level of the one or more erase pulses applied to the one or more memory cells of the sample of memory cells during the subsequent erase operation comprises adjusting the erase starting voltage level of the one or more erase pulses applied to the one or more memory cells of the sample of memory cells during the subsequent erase operation to reduce the number of erase pulses applied to the one or more memory cells of the sample of memory cells during the subsequent erase operation when the determined number of erase pulses required for erasing the sample of memory cells in the prior erase operation exceeds the target number.
10. A memory device, comprising: a memory array; a state machine configured to control erase operations on the memory array and to determine a number of erase pulses required to erase one or more memory cells of the memory array; starting-voltage level control logic coupled to the state machine, the starting-voltage level control logic configured to adjust an erase starting voltage level of one or more erase pulses applied to one or more memory cells during an erase operation in response, at least in part, to a number of erase pulses required for erasing one or more memory cells during a previous erase operation; and a sampling circuit in communication with the starting-voltage level control logic and the state machine, the sampling circuit configured to determine a number of erase pulses it takes to erase a sample of one or more memory cells, wherein the sample of erased memory cells includes the one or more memory cells erased during the previous erase operation.
11. The memory device of claim 10 , wherein the starting-voltage level control logic is configured to determine an average number of erase pulses it takes to erase the sample of erased memory cells.
12. The memory device of claim 10 , wherein the starting-voltage level control logic comprises a latch configured to store the number of erase pulses required for erasing the one or more memory cells erased during the previous erase operation.
13. The memory device of claim 10 , wherein the one or more memory cells erased during the previous erase operation include the one or more memory cells to which the one or more erase pulses with the adjusted erase starting voltage level are being applied.
14. The memory device of claim 10 , wherein the one or more memory cells erased during the previous erase operation do not include the one or more memory cells to which the one or more erase pulses with the adjusted erase starting voltage level are being applied.
15. The memory device of claim 10 , wherein the starting-voltage level control logic is further configured to compare the number of erase pulses required for erasing the one or more memory cells erased during the previous erase operation to a target number of erase pulses.
16. The memory device of claim 15 , wherein the starting-voltage level control logic is further configured to adjust the erase starting voltage level of the one or more erase pulses when the number of erase pulses required for erasing the one or more memory cells erased during the previous erase operation exceeds the target number of erase pulses by some number greater than one.
17. The memory device of claim 10 , further comprising a high-voltage regulator coupled to the starting-voltage level control logic for receiving the erase starting voltage level of the one or more erase pulses from the starting-voltage level control logic, wherein a trim of the high-voltage regulator is configured to be set to an erase starting voltage in response to the erase starting voltage level of the one or more erase pulses received from the starting-voltage level control logic.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 16, 2010
June 5, 2012
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