Methods and apparatus for single stage Galois field operations

1. An apparatus for computing a GF (2 m ) multiplication, where m is a positive integer, the apparatus comprising: means to calculate a portion of the GF (2 m ) multiplication in a GF multiplication circuit cell; means to interconnect an m-by-m array of GF multiplication circuit cells; means to connect a plurality of inputs to the m-by-m array, wherein the m-by-m array of GF multiplication circuit cells is constructed by replicating the GF multiplication circuit cell in a regular m-by-m organization and interconnecting the m-by-m array of GF multiplication circuit cells according to the equation Y(i)=Y(i−1)+(q m-1 *p+Y(−1) m-1 *g)*x m-i , i=1, 2, . . . , m for m bits in input operands q m-i , and p, set g is coefficients of a generator polynomial g[x], Y(0)=0, and Y(i=m) is an m bit result of the GF(2 m ) multiplication; and means for storing the m bit result of the GF (2 m ) multiplication.

2. The apparatus of claim 1 , wherein each GF multiplication circuit cell of the m-by-m array of GF multiplication circuit cells comprises: an AND gate producing q m-i AND p j as output A, wherein iε{1, 2, . . . , m}, jε{0, 1, . . . . , m−1}, where m is a positive integer that indicates the number of bits in the result of the GF (2 m ) multiplication, the input operand q m-i is a bit selected from a first input set {q m-1 , q m-2 , . . . , q m-i , . . . , q 0 } based on a selected i value, and p j is a bit selected from the input operand p equal to a second input set {p m-1 , p m-2 , . . . , p j , . . . , p 0 } based on a selected j value; an AND gate producing Y(i−1) m-1 AND g j as output B, wherein Y(i−1) m-1 for i−1≠0 is a most significant bit of a previous stage of the m-by-m array of GF multiplication circuit cells results and g j is a bit selected from the set g equal to a third input set {g m-1 , g m-2 , . . . , g j , . . . , g 0 } of generator polynomial coefficients based on the selected j value; and an Exclusive OR gate producing A XOR B XOR Y(i−1) j-1 as result Y(i) j for i≠m to be utilized in the next stage of the m-by-m array of GF multiplication circuit cells and result Y(i) j for i=m to be stored in a processor-accessible storage unit that is part of the means for storing the m bit result, wherein Y(i−1) j-1 is a rightmost neighbor bit of a previous stage of GF multiplication circuit cells results, wherein the rightmost neighbor bit Y(i−1) j-1 is in relation to the present GF multiplication circuit cell producing result Y(i) j for each of the selected and j values.

3. The apparatus of claim 2 , wherein the m-by-m array of GF multiplication circuit cells is organized in m rows, each row having m GF multiplication circuit cells, wherein the Y(i−1) m-1 bit of each of the m GF multiplication circuit cells in a first row associated with the input operand q m-1 bit, is connected to a first value and in succeeding rows, each row associated with a corresponding input operand q m-2 , . . . , q m-i , . . . , g o bit, the Y(i−1) m-1 bit of each of the m GF multiplication circuit cells in each row is connected to a most significant bit of a previous row of GF multiplication circuit cells results and wherein the Y(i−1) j-1 bit of each of the m GF multiplication circuit cells in the first row associated with the input operand q m-1 bit, is connected to a second value, in the succeeding rows, each row associated with the corresponding input operand q m-2 , . . . . , q m-i , . . . , q 0 bit, the bit of the m GF multiplication circuit cells in each row is connected to the rightmost neighbor bit of the previous row of GF multiplication circuit cell results, and in a column associated with j=0 the Y(i−1) j-1 bit of each GF multiplication circuit cells is connected to a third value.

4. The apparatus of claim 3 , wherein the first value, the second value, and the third value are set to a value of zero.

5. The apparatus of claim 2 , wherein means to connect the plurality of inputs to the m-by-m array comprises: a first register having a first output port of at least length m bits that is connected to corresponding bits from the first input set {q m-1 , q m-2 , . . . q 0 }; a second register having a second output port of at least length m bits that is connected to corresponding bits from the second input set {p m-1 , p m-2 , . . . , p 0 }; and a third register having a third output port of at least length m bits that is connected to corresponding bits from the third input set {g m-1 , g m-2 , . . . , g 0 }.

6. The apparatus of claim 5 , wherein the first register and the second register are registers from a general purpose register file of a processor and the third register is a register separate from the register file, wherein the first register, the second register, and the third register are loaded under program control.

7. The apparatus of claim 2 , wherein means for storing the m bit result comprises: a result target register having an input port of at least length m bits that is connected to corresponding bits of the result Y(i=m) j for each of the selected j values, wherein the result Y(i=m) j is stored in the result target register that is selected from a general purpose register file under program control.

8. A computer-readable non-transitory medium whose contents cause a computer system to perform at least one GF multiplication, the computer system including a program storage unit wherein at least one GF multiplication instruction is stored, a plurality of processing elements (PEs), means to distribute the at least one GF multiplication instruction fetched from the program storage unit to the plurality of PEs, and wherein each PE comprises program execution means including at least one m-by-m array of GF multiplication circuit cells which execute the distributed GF multiplication instruction received in said each PE, whereby more than one GF multiplication is accomplished in parallel, wherein said computer system performs: fetching the at least one GF multiplication instruction from the program storage unit; and executing the distributed GF multiplication instruction whereby the computer system performs at least one GF (2 m ) multiplication in each PE by the program execution means.

9. The computer readable non-transitory medium of claim 8 , wherein the at least one GF multiplication is computed by the m-by-m array of GF multiplication circuit cells to produce result Y(m) according to a GF multiplication function Y(i)=Y(i−1)+(q m-i *p+Y(−1) m-1 *g)*x m-i , iε{1, 2, . . . , m} and where Y(0)=0, Y(i=m) is the m bit GF multiplication result, p and q are coefficients of input polynomials p[x] and q[x], respectively, that have been separately stored in two registers of a register file, and g is coefficients of a generator polynomial g[x] that has been stored in a third register.

10. The computer readable non-transitory medium of claim 9 , wherein the GF multiplication instruction specifies a selection of the two registers to provide p and q to the m-by-m array of GF multiplication circuit cells and g is provided by connecting the third register to the m-by-m array of GF multiplication circuit cells.

11. A method for executing at least one GF multiplication instruction contained in a very long instruction word (VLIW) on a computer system having VLIW execution means including a plurality of processing elements (PEs), wherein each PE of the plurality of PEs comprises a VLIW storage unit, at least one m-by-m array of GF multiplication circuit cells, and means to invoke a VLIW containing a GF multiplication instruction on said each PE of said plurality of PEs in parallel, wherein said each PE of said plurality of PEs executes a GF multiplication instruction, and wherein said means to invoke a VLIW containing said GF multiplication instruction accomplishes more than one GF multiplication in parallel, the method comprising: fetching the VLIW from the VLIW storage unit in said each PE of said plurality of PEs; and executing the fetched VLIW including the GF multiplication instruction in said each PE of said plurality of PEs, whereby the computer system performs at least one GF (2 m ) multiplication in said each PE of said plurality of PEs by the VLIW execution means.

12. The method of claim 11 wherein the at least one GF (2 m ) multiplication is computed by a logic circuit to produce result Y(m) in said each PE of said plurality of PEs according to a GF multiplication function Y(i)=Y(i−1)+(q m-i *p+((i−1) m-1 *g)*x m-i , iε{1, 2, . . . , m} and where Y(0)=0, Y(i=m) is the m bit GF multiplication result, p and q are input sets of coefficients of input polynomials p[x] and q[x], respectively, and g is the coefficients of a generator polynomial g[x].

13. The method of claim 12 , wherein the GF multiplication instruction comprises a first bit field for selecting a first register having bits corresponding to the input set q={q m-1 , q m-2 , . . . , q 0 }, a second bit field for selecting a second register having bits corresponding to the input set p={p m-1 , p m-2 , . . . , p 0 }, and a third bit field for selecting a third register having bits corresponding to the m bit GF multiplication result Y(i=m), wherein m is an integer representing the length of the first register, the second register, and the third register and g is pre-specified prior to issuing the GF multiplication instruction.

14. The method of claim 12 wherein the GF multiplication instruction comprises a first bit field for selecting a first register that is partitioned into a plurality of first sub-registers, each of the first sub-registers of said plurality of first sub-registers having bits corresponding to an input set q={q m-1 , q m-2 , . . . , q 0 } for each m-by-m array of a plurality of m-by-m arrays of GF multiplication circuit cells, a second bit field for selecting a second register that is partitioned into a plurality of second sub-registers, each of the second sub-registers of said plurality of second sub-registers having bits corresponding to an input set p={p m-1 , p m-2 , . . . , p 0 } for each of the m-by-m arrays of said plurality of m-by-m arrays of GF multiplication circuit cells, and a third bit field for selecting a third register that is partitioned into a plurality of third sub-registers, each of the third sub-registers of said plurality of third sub-registers having bits corresponding to an m bit result Y(m) for each of the m-by-m arrays of said plurality of m-by-m arrays of GF multiplication circuit cells, wherein m is an integer representing the length of each of the sub-registers and g is pre-specified prior to issuing the GF multiplication instruction, whereby more than one GF multiplication is accomplished in parallel.

15. The method of claim 14 wherein a first encoding of the GF multiplication instruction specifies four first sub-registers, four second sub-registers and four third sub-registers, and wherein a second encoding of the GF multiplication instruction specifies eight first sub-registers, eight second sub-registers, and eight third sub-registers.

16. The method of claim 11 wherein the VLIW execution means further comprises: said each PE of said plurality of PEs having a plurality of m-by-m arrays of GF multiplication circuit cells; and means to invoke a VLIW containing a GF multiplication instruction on said each PE of said plurality of PEs in parallel whereby more than one GF multiplication is accomplished in parallel in said each PE of said plurality of PEs.

17. The method of claim 11 , wherein the means to invoke a VLIW comprises: fetching an execute VLIW instruction from a program storage unit associated with a controller of the plurality of PEs; distributing the execute VLIW instruction to the plurality of PEs; fetching the VLIW containing the GF multiplication instruction from the VLIW storage unit located on said each PE of the plurality of PEs; and executing the GF multiplication instruction as part of the execution of the VLIW on said each PE of the plurality of PEs.