A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of storing multiple bits of information including multiple pages of information and is allocated to a plurality of threshold voltage distributions; and a control circuit configured to write information to a memory cell by applying a voltage to a bit line and a word line to change a threshold voltage of the memory cell. During writing of information to a plurality of the memory cells connected to an identical word line, the control circuit is configured to apply, to each of the bit lines corresponding to the plurality of the memory cells, any one of voltages that differ from one another according to the multiple bits of information to be written.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of storing multiple bits of information including multiple pages of information and is allocated to a plurality of threshold voltage distributions; and a control circuit configured to write information to a memory cell by applying a voltage to a bit line and a word line to change a threshold voltage of the memory cell, during writing of information to a plurality of the memory cells connected to an identical word line, the control circuit being configured to apply, to each of the bit lines corresponding to the plurality of the memory cells, any one of voltages that differ from one another according to the multiple bits of information to be written.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein the control circuit comprises a bit-line-clamp-transistor having one end connected to the bit line to clamp a voltage of the bit line when a clamp voltage is applied to a gate thereof, and wherein the control circuit lowers a value of the clamp voltage from a first value to a second value in a number of steps corresponding to a number of bits stored by one of the memory cells.
3. The nonvolatile semiconductor memory device according to claim 1 , wherein the control circuit applies the voltages to the bit line such that the greater a voltage value of the threshold voltage distribution of information to be written to the memory cells, the smaller the voltage applied to the bit line is set.
4. The nonvolatile semiconductor memory device according to claim 1 , wherein the control circuit further comprises: a data latch circuit configured to retain data of one page out of the multiple pages as information to be written to the memory cells; and an arithmetic circuit configured to perform a logical operation on the multiple pages of information retained in the data latch circuit, and wherein the control circuit applies a different voltage to the bit line based on an operation result of the arithmetic circuit.
5. The nonvolatile semiconductor memory device according to claim 1 , wherein the memory cell array is configured by an arrangement of NAND cell units, each of the NAND cell units having a plurality of the memory cells connected in series.
6. The nonvolatile semiconductor memory device according to claim 1 , wherein the control circuit, when applying any one of the voltages to the bit line, applies the voltages sequentially from a voltage with a high voltage value.
7. The nonvolatile semiconductor memory device according to claim 1 , wherein the control circuit writes information to the memory cells by applying a write voltage to the word line multiple times.
8. The nonvolatile semiconductor memory device according to claim 7 , wherein the control circuit performs a write operation by stepping up a voltage value of the write voltage applied to the word line.
9. A nonvolatile semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of storing multiple bits of information including multiple pages of information and is allocated to a plurality of threshold voltage distributions; and a control circuit configured to write information to a memory cell by applying a voltage to a bit line and a word line to change a threshold voltage of the memory cell, the control circuit comprising: a data latch circuit configured to retain data of one page out of the multiple pages as information to be written to the memory cells; an arithmetic circuit configured to perform a logical operation on the multiple pages of information retained in the data latch circuit; a sense amplifier circuit configured to control a voltage of a first node based on an operation result of the arithmetic circuit; and a bit-line-clamp-transistor having one end connected to the bit line and another end connected to the first node and configured to clamp a voltage of the bit line when a clamp voltage is applied to a gate thereof, during writing of information to a plurality of the memory cells connected to an identical word line, the control circuit being configured to apply a voltage to the first node using the sense amplifier circuit and change a value of the clamp voltage, thereby apply, to each of the bit lines corresponding to the plurality of the memory cells, any one of voltages that differ from one another according to the multiple bits of information to be written.
10. The nonvolatile semiconductor memory device according to claim 9 , wherein the control circuit, while maintaining the voltage of the first node, lowers a value of the clamp voltage from a first value to a second value in a number of steps corresponding to a number of bits stored by one of the memory cells.
11. The nonvolatile semiconductor memory device according to claim 9 , wherein the control circuit applies the voltages to the bit line such that the greater a voltage value of the threshold voltage distribution of information to be written to the memory cells, the smaller the voltage applied to the bit line is set.
12. The nonvolatile semiconductor memory device according to claim 9 , wherein the memory cell array is configured by an arrangement of NAND cell units, each of the NAND cell units having a plurality of the memory cells connected in series.
13. The nonvolatile semiconductor memory device according to claim 9 , wherein the control circuit, when applying any one of the voltages to the bit line, applies the voltages sequentially from a voltage with a high voltage value.
14. The nonvolatile semiconductor memory device according to claim 9 , wherein the control circuit writes information to the memory cells by applying a write voltage to the word line multiple times.
15. The nonvolatile semiconductor memory device according to claim 14 , wherein the control circuit performs a write operation by stepping up a voltage value of the write voltage applied to the word line.
16. A method of operating a nonvolatile semiconductor memory device, the nonvolatile semi conductor memory device including a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of storing multiple bits of information including multiple pages of information and is allocated to a plurality of threshold voltage distributions, and a control circuit configured to write information to a memory cell by applying a voltage to a bit line and a word line to change a threshold voltage of the memory cell, comprising: during writing of information to a plurality of the memory cells connected to an identical word line, applying, to each of the bit lines corresponding to the plurality of the memory cells, any one of voltages that differ from one another according to the multiple bits of information to be written; and applying a write voltage to the word line multiple times to write information to the memory cells.
17. The method of operating a nonvolatile semiconductor memory device according to claim 16 , wherein the voltages are applied to the bit lines such that the greater a voltage value of the threshold voltage distribution of information to be written to the memory cells, the smaller the voltage applied to the bit line is set.
18. The method of operating a nonvolatile semiconductor memory device according to claim 16 , wherein the control circuit further comprises: a data latch circuit configured to retain data of one page out of the multiple pages as information to be written to the memory cells; and an arithmetic circuit configured to perform a logical operation on the multiple pages of information retained in the data latch circuit, and wherein data of one page as information is inputted to the data latch circuit, the operation is executed by the arithmetic circuit based on information of the data latch circuit, and a different voltage is applied to the bit line based on an operation result of the arithmetic circuit.
19. The method of operating a nonvolatile semiconductor memory device according to claim 16 , wherein, when any one of the voltages are applied to the bit lines, the voltages are applied sequentially from a voltage with a high voltage value.
20. The method of operating a nonvolatile semiconductor memory device according to claim 16 , wherein a write operation is performed by stepping up a voltage value of the write voltage applied to the word line.
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March 10, 2010
August 7, 2012
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