Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data driver circuit, comprising: a data capture circuit configured to receive a data signal responsive to a write strobe signal, the data capture circuit configured to capture a first digit of the data signal responsive to a first edge of the strobe signal and at least a second digit of the data signal responsive to a second edge of the strobe signal; and a write control circuit coupled to the data capture circuit and further coupled to receive an external timing signal and the write strobe signal, the write control circuit configured to determine which digit of the data signal was latched first relative to the external timing signal, and generate a select signal to drive the first and at least second digits of the data signal latched in the data capture circuit onto a bus in the order the digits of the data signal were received.
2. The data driver circuit of claim 1 wherein the write strobe signal comprises a discontinuous clock signal and the external timing signal comprises a continuous clock signal.
3. The data driver circuit of claim 1 wherein the write control circuit comprises a clock divider circuit coupled to receive the write strobe signal and coupled to the data capture circuit, the clock divider circuit configured to divide the write strobe signal to generate a plurality of write strobe signals, each of the plurality of write strobe signals having a different clock phase relative to each other.
4. The data driver circuit of claim 3 wherein the data capture circuit comprises: a plurality of data capture latches coupled to receive the plurality of write strobe signals and each digit of the received data signal, the plurality of data capture latches configured to phase-split a corresponding clock signal of the plurality of divided write strobe signals the plurality of data capture latches between rising edge data and falling edge data; and a plurality of demultiplexer circuits coupled respectively to the plurality of data capture latches and to the bus, each of the plurality of demultiplexer circuits further coupled to receive the plurality of write strobe signals having different phases, and configured to latch and track the digits of the received data signal.
5. The data driver circuit of claim 4 wherein the plurality of demultiplexer circuits comprise a plurality of Muller gates each having an output coupled to a respective latch in the plurality of data capture latches, the plurality of Muller gates configured to close the respectively coupled latch responsive to the latch receiving a corresponding digit of the data signal and responsive to a logic transition of the Muller gate output.
6. The data driver circuit of claim 5 wherein the plurality of Muller gates are further configured to receive a reset signal from a reset circuit in the write control circuit, the reset circuit operable to generate the reset signal responsive to at least one of the plurality of clock signals having different phases.
7. The data driver circuit of claim 1 , wherein the data capture circuit is further configured to provide a latch control signal to the write control circuit relative to when each digit of data signal is captured.
8. A data driver circuit, comprising: a data latch circuit coupled to a bus and configured to latch write data based, at least in part, on a clock signal; a demultiplexer control circuit coupled to the data latch circuit and configured to capture the latched write data responsive to the clock signal; and a write control circuit coupled to the demultiplexer control circuit and configured to receive a plurality of latch signals, the write control circuit further configured to provide a plurality of output signals to the demultiplexer control circuit based, at least in part, on a plurality of latch signals; wherein the demultiplexer control circuit is configured to provide the latched write data to a bus in an order the latched write data was captured responsive, at least in part, to receipt of the plurality of output signals.
9. The data driver circuit of claim 8 , further comprising: a clock divider coupled to the data capture circuit and the demultiplexer control circuit and configured to provide the clock signal, wherein the clock signal is based, at least in part, on a write strobe signal.
10. The data driver circuit of claim 8 , further comprising: an input path coupled to the data latch circuit and configured to delay the write data.
11. The data driver circuit of claim 8 , wherein the demultiplexer control circuit is configured to provide the plurality of latch signals responsive, at least in part, to capturing the latched write data.
12. The data driver circuit of claim 11 , wherein the write control circuit is further configured to provide the plurality of output signals based, at least in part, on an external clock signal.
13. The data driver circuit of claim 8 , wherein the write control circuit is further configured to determine the order in which the latched write data was captured by the demultiplexer control circuit.
14. The data driver circuit of claim 8 , wherein the data latch circuit is configured to capture the write data based, at least in part, on rising and falling edges of the clock signal.
15. The data driver circuit of claim 8 , wherein the data latch circuit is configured to phase split the respective write data.
16. A data driver circuit, comprising: a plurality of data latch circuits each configured to latch a respective data signal responsive to a clock signal; a plurality of demultiplexer control circuits each coupled to a respective one of the plurality of data latch circuits and configured to capture the respective latched data signal responsive to the clock signal; wherein one of the plurality of demultiplexer control circuits comprises a feedback demultiplexer control circuit and is configured to generate a plurality of latch control signals responsive, at least in part, to capturing the respective latched data signal, wherein each of the plurality of demultiplexer control circuits is configured to provide the respective latched data signal to a bus based, at least in part, on a timing of the plurality of latch control signals relative to an external clock signal.
17. The data driver circuit of claim 16 , wherein each of the plurality of data latch circuits is configured to capture the respective data signal based, at least in part, on rising and falling edges of the clock signal.
18. The data driver circuit of claim 16 , further comprising: a clock divider coupled to each of the plurality of data capture circuits and configured to provide the clock signal, wherein the clock signal is based, at least in part, on a write strobe signal.
19. The data driver circuit of claim 16 , wherein each of the plurality of data latch circuits comprises a latch configured to phase split the respective data signal.
20. The data driver circuit of claim 16 , wherein each of the plurality of demultiplexer control circuits is configured to provide bits of the respective latched data signal in an order determined by a write control circuit.
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April 3, 2012
October 9, 2012
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