Disclosed is a memory module having an ElectroStatic Discharge (ESD) prevention structure. The memory module may include a printed circuit board, a first circuit pattern on the printed circuit board, and a second circuit pattern on the printed circuit board. The second circuit pattern may be configured to discharge static electricity introduced to the memory module from outside the memory module. In addition, the second circuit pattern is not connected to the first circuit pattern. Disclosed also is a system that includes the memory module. The system may include a main board, a socket on the main board, and the memory module.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory module having an ElectroStatic Discharge (ESD) prevention structure, the memory module comprising: a printed circuit board; a first circuit pattern on the printed circuit board; a second circuit pattern on the printed circuit board, the second circuit pattern configured to discharge static electricity introduced to the memory module from outside the memory module, the second circuit pattern not being connected to the first circuit pattern and being along an outer edge of the printed circuit board; and at least one capacitor on the second circuit pattern, the at least one capacitor connected to the second circuit pattern and configured to store the static electricity.
2. The memory module of claim 1 , wherein the second circuit pattern is a conductive material and is exposed to the outside.
3. The memory module of claim 1 , further comprising: at least one memory device connected to the first circuit pattern.
4. The memory module of claim 3 , wherein the first circuit pattern is partially covered by the at least one memory device.
5. The memory module of claim 1 , wherein the printed circuit board includes a nonconductive layer covering the first circuit pattern and the second circuit pattern is on the nonconductive layer.
6. The memory module of claim 1 , wherein the first circuit pattern is in a shielded state and the second circuit pattern is in an exposed state.
7. The memory module of claim 1 , wherein the printed circuit board is multi-layered and the first circuit pattern is formed therewithin.
8. A system comprising: a main board on which a plurality of electronic components are mounted; a socket on the main board; and a memory module in the socket and connected to the main board via the socket, wherein the memory module includes a printed circuit board, a first circuit pattern on the printed circuit board, a second circuit pattern on the printed circuit board, the second circuit pattern configured to discharge static electricity introduced to the memory module from outside the memory module, the second circuit pattern not being connected to the first circuit pattern and being along an outer edge of the printed circuit board, and at least one capacitor on the second circuit pattern, the at least one capacitor connected to the second circuit pattern and configured to store the static electricity.
9. The system of claim 8 , wherein the second circuit pattern is connected to a ground pattern of the main board via the socket, wherein the static electricity is discharged into the ground pattern of the main board from the second circuit pattern and the socket.
10. The system of claim 8 , wherein the second circuit pattern conducts the static electricity from the at least one capacitor to a ground pattern on the main board.
11. The system of claim 8 , wherein the second circuit pattern is an exposed conductive material.
12. The system of claim 8 , wherein the memory module further includes a memory device on the printed circuit board.
13. The system of claim 8 , wherein the printed circuit board includes a nonconductive layer covering the first circuit pattern and the second circuit pattern is on the nonconductive layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 31, 2010
October 16, 2012
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