Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may include a first logic gate that receives the clock signal at an input port and receives first control signals, and pull-up circuits in communication with an output of the first logic gate and first control signals. A second logic gate receives the clock signal at the input port and receives second control signals. Pull-down circuits are coupled to the second logic gate and the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to the output port to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A selective edge phase mixing apparatus, comprising: a first logic gate to receive a clock signal and a first control signal; at least one pull-up circuit having a pull-up device and a pull-up enable device coupled to an output of the first logic gate; a second logic gate to receive the clock signal, and to receive a second control signal; and at least one pull-down circuit having a pull-down device and a pull-down enable device coupled to an output of the second logic gate, wherein the pull-up and the pull-down circuits communicate with an output that provides a duty cycle corrected version of the clock signal.
2. The apparatus of claim 1 , wherein the pull-up device and the pull-up enable device include serially-coupled pFET devices, and the pull-up device is coupled to a supply potential.
3. The apparatus of claim 1 , wherein the pull-down device and the pull-down enable device include serially-coupled nFET devices, and the pull-down device is coupled to a ground potential.
4. The apparatus of claim 1 , wherein the first logic gate includes at least a pair of serially-coupled NOT gates.
5. The apparatus of claim 1 , wherein the second logic gate includes at least a pair of serially-coupled NOT gates.
6. The apparatus of claim 1 , wherein the first logic gate includes at least a NOT gate operably coupled to a NAND gate.
7. The apparatus of claim 1 , wherein the second logic gate includes at least a NOT gate operably coupled to a NAND gate.
8. A selective edge phase mixing apparatus, comprising: a first logic gate responsive to a subtract duty (SD) control signal; a pull-up interpolation circuit coupled to the first logic gate and responsive to the SD control signal; a second logic gate responsive to an add duty (AD) control signal; and a pull-down interpolation circuit coupled to the second logic gate and responsive to the AD control signal, wherein the pull-up and the pull-down interpolation circuits communicate with an output of the apparatus that provides a duty cycle corrected clock signal when the first and second logic gates are operably coupled to the SD and the AD control signals, respectively.
9. The apparatus of claim 8 , wherein the first logic gate or the second logic gate includes at least one NAND gate operably coupled to a NOT gate.
10. The apparatus of claim 8 , wherein the pull-up interpolation circuit includes a pull-up device and a pull-up enable device.
11. The apparatus of claim 10 , wherein the pull-up device comprises a pFET device.
12. The apparatus of claim 10 , wherein the pull-up enable device is coupled to the SD control signal.
13. The apparatus of claim 8 , wherein the pull-down interpolation circuit includes a pull-down device and a pull-down enable device.
14. The apparatus of claim 13 , wherein the pull-down device comprises an nFET device.
15. The apparatus of claim 13 , wherein the pull-down enable device is coupled to the AD control signal.
16. A method, comprising: receiving a non-adjusted clock signal at an input; receiving at least one duty cycle adjustment signal generated by an edge phase mixing apparatus that includes a first logic gate and a second logic gate coupled to the input, wherein the first logic gate is responsive to a subtract duty (SD) control signal, and wherein the second logic gate is responsive to an add duty (AD) control signal; and adjusting a duty cycle of the non-adjusted clock signal in response to the received duty cycle adjustment signal, to provide an adjusted clock signal.
17. The method of claim 16 , wherein receiving at least one duty cycle adjustment signal comprises receiving first order signals and higher order signals to selectively increase or decrease the duty cycle of the non-adjusted clock signal.
18. The method of claim 16 , wherein adjusting the duty cycle of the non-adjusted clock signal comprises enabling a pull-up interpolation circuit to affect a falling edge of the non-adjusted clock signal to increase the duty cycle.
19. The method of claim 16 , wherein adjusting the duty cycle of the non-adjusted clock signal comprises enabling a pull-down interpolation circuit to affect a rising edge of the non-adjusted clock signal to increase the duty cycle.
20. The method of claim 16 , comprising providing a buffered version of the adjusted clock signal to an external device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 15, 2011
October 16, 2012
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