Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device structure, comprising: a substrate; at least one via hole extending partially through the substrate; and a dielectric coating over surfaces of the at least one via hole, the dielectric coating including: at least one adhesion material; and a dielectric material different from the at least one adhesion material and having a dielectric constant (K) of about 2.
2. The semiconductor device structure of claim 1 , wherein the at least one adhesion material of the dielectric coating comprises an oxide.
3. The semiconductor device structure of claim 1 , wherein the at least one adhesion material contacts surfaces of the at least one via hole.
4. The semiconductor device structure of claim 3 , wherein the dielectric material coats the at least one adhesion layer.
5. The semiconductor device structure of claim 4 , further comprising: another adhesion material different from the dielectric material and coating the dielectric material.
6. The semiconductor device structure of claim 1 , wherein the at least one adhesion material coats the dielectric material.
7. The semiconductor device structure of claim 1 , wherein the at least one via hole extends through a bond pad carried by the substrate.
8. The semiconductor device structure of claim 7 , wherein the dielectric coating extends onto at least a portion of an edge of the bond pad that is continuous with the at least one via hole.
9. A semiconductor device structure, comprising: a substrate comprising semiconductor material; at least one via hole extending partially through semiconductor material of the substrate and including at least one roughened surface with an enhanced surface area; and a dielectric coating over the at least one roughened surface comprising a dielectric material having a dielectric constant (K) of about 2.
10. The semiconductor device structure of claim 9 , wherein the at least one via hole extends through a bond pad carried by the substrate.
11. The semiconductor device structure of claim 10 , wherein the dielectric coating extends onto at least a portion of an edge of the bond pad that is continuous with the at least one via hole.
12. The semiconductor device structure of claim 9 , further comprising an aluminum material over the dielectric coating.
13. A semiconductor device structure, comprising: a substrate comprising semiconductor material; at least one via hole extending at least partially through semiconductor material of the substrate; a dielectric coating over a surface of the at least one via hole, the dielectric coating including: at least one adhesion material; and a dielectric material different from the at least one adhesion material; seed material on at least a portion of the dielectric coating over the surface of the at least one via hole; and a conductive material different from and coating the seed material.
14. The semiconductor device structure of claim 13 , wherein the dielectric coating comprises a low-K dielectric material.
15. The semiconductor device structure of claim 13 , further comprising: a barrier layer between the seed material and at least the portion of the surface of the at least one via hole.
16. The semiconductor device structure of claim 15 , wherein the barrier layer comprises at least one of titanium, titanium nitride, tantalum, and tantalum nitride.
17. The semiconductor device structure of claim 13 , wherein the conductive material comprises copper.
18. The semiconductor device structure of claim 13 , wherein the seed material comprises aluminum.
19. The semiconductor device structure of claim 18 , wherein the at least one via hole extends through a bond pad carried by the substrate.
20. The semiconductor device structure of claim 19 , wherein the bond pad comprises an unplated bond pad.
21. The semiconductor device structure of claim 20 , wherein the seed material contacts an unplated surface of the unplated bond pad.
22. The semiconductor device structure of claim 18 , wherein the conductive material comprises nickel.
23. The semiconductor device structure of claim 13 , further comprising: a void between opposed surfaces of the conductive material.
24. The semiconductor device structure of claim 23 , further comprising: a polymeric dielectric filler material within the void.
25. The semiconductor device structure of claim 24 , wherein a surface of the polymeric dielectric filler material is substantially coplanar with a surface of the substrate.
26. A semiconductor device structure, comprising: a substrate; at least one via hole extending at least partially through the substrate; seed material on at least a portion of the surface of the at least one via hole; a conductive material different from and coating the seed material; a void between opposed surfaces of the conductive material; and a polymeric dielectric filler material within the void.
27. The semiconductor device structure of claim 26 , wherein a surface of the polymeric dielectric filler material is substantially coplanar with a surface of the substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 6, 2011
October 23, 2012
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