A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A chip package, comprising: a semiconductor substrate having a first surface and a second surface; a device region or sensing region and a conducting pad disposed on the first surface; a hole extending from the second surface to the conducting pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface and the insulating layer; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the conducting pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on a surface of the carrier substrate, extending towards the second surface along the sidewall formed by the carrier substrate and the insulating layer, and electrically contacting the exposed edge of the first redistribution layer; and a buffer layer located on the second surface of the semiconductor substrate and located between the second redistribution layer and the semiconductor substrate such that the second redistribution layer does not directly contact with the semiconductor substrate.
2. The chip package as claimed in claim 1 , wherein a position of an inverted point of the first redistribution layer extending from the sidewall of the hole to the second surface is not coplanar with a contact position between the first redistribution layer and the second redistribution layer, wherein the buffer layer is located on the second surface.
3. The chip package as claimed in claim 1 , wherein an adhesion layer is between the carrier substrate and the insulating layer, the adhesion layer directly contacts with the carrier substrate, and a contact interface between the adhesion layer and the carrier substrate is substantially planar.
4. The chip package as claimed in claim 3 , further comprising a filling layer located between the adhesion layer and the first redistribution layer.
5. The chip package as claimed in claim 4 , wherein the filling layer substantially and completely fills the hole.
6. The chip package as claimed in claim 1 , further comprising an ESD protecting layer located on the first surface of the semiconductor substrate, wherein the ESD protecting layer does not cover the device region or sensing region.
7. The chip package as claimed in claim 6 , wherein the ESD protecting layer does not cover the conducting pad.
8. The chip package as claimed in claim 6 , further comprising a passivation layer covering the semiconductor substrate, the device region or sensing region, the conducting pad, and the ESD protecting layer, wherein a material of the passivation layer is a material solidified from an adhesive glue.
9. A chip package, comprising: a semiconductor substrate having a first surface and a second surface; a device region or sensing region located on or in the semiconductor substrate; a conducting pad located on or in the semiconductor substrate and electrically connected to the device region or sensing region; a hole extending from the second surface towards the first surface and exposing the conducting pad; an insulating layer located on a sidewall of the hole; a redistribution layer located in the hole and electrically connected to the conducting pad; and a conducting layer located between the redistribution layer and the conducting pad.
10. The chip package as claimed in claim 9 , wherein a material of the conducting layer is different from a material of the redistribution layer.
11. The chip package as claimed in claim 9 , wherein a portion of the insulating layer is located on a bottom of the hole to cover a portion of the conducting pad, and the conducting layer electrically contacts with an exposed portion of the conducting pad.
12. The chip package as claimed in claim 11 , wherein a thickness of the conducting layer is larger than a thickness of the insulating layer located on the bottom of the hole.
13. The chip package as claimed in claim 9 , further comprising an ESD protecting layer located on the first surface of the semiconductor substrate, wherein the ESD protecting layer does not cover the device region or sensing region.
14. The chip package as claimed in claim 13 , wherein the ESD protecting layer does not cover the conducting pad.
15. The chip package as claimed in claim 13 , further comprising a passivation layer covering the semiconductor substrate, the device region or sensing region, the conducting pad, and the ESD protecting layer, wherein a material of the passivation layer is a material solidified from an adhesive glue.
16. A chip package, comprising: a chip having a first side and a second side and having an upper surface and a lower surface, wherein the first side is larger than the second side; a plurality of first conducting pads arranged along the first side; a plurality of first trench openings arranged along the first side and extending from the lower surface towards the upper surface; a plurality of first redistribution layers, respectively, and correspondingly, located on a sidewall of one of the first trench openings and electrically connected to one of the first conducting pads; a plurality of second conducting pads arranged along the second side; a plurality of second trench openings arranged along the second side and extending from the lower surface towards the upper surface; a plurality of second redistribution layers, respectively, and correspondingly, located on a sidewall of one of the second trench openings and electrically connected to one of the second conducting pads; and a light sensitive insulating layer covering the lower surface of the chip, wherein a total amount of the light sensitive insulating layer filled into the first trench openings is smaller than or equal to a total amount of the light sensitive insulating layer filled into the second trench openings.
17. The chip package as claimed in claim 16 , wherein the light sensitive insulating layer is not completely filled into the first trench openings or the second trench openings.
18. The chip package as claimed in claim 16 , wherein a thickness of a portion of the light sensitive insulating layer filled into the first trench openings is smaller than a thickness of a portion of the light sensitive insulating layer filled into the second trench openings.
19. The chip package as claimed in claim 16 , further comprising an ESD protecting layer located on the first surface of the semiconductor substrate, wherein the ESD protecting layer does not cover the device region or sensing region.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 11, 2011
October 23, 2012
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