A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a silicon wafer, comprising: preparing a wafer having a front surface, a rear surface and a rim edge connecting the front and rear surfaces; generating embryos, which become oxygen precipitates by succeeding annealing, in the silicon wafer; stabilizing the embryos generated in the silicon wafer; and removing defects and the embryos existing within a predetermined depth from the front and rear surfaces of the silicon wafer, after the step of stabilizing the embryos, wherein the step of generating embryos is conducted in a way of thermally annealing the silicon wafer at a first temperature, wherein the step of stabilizing the embryos is conducted in a way of thermally annealing the silicon wafer with the embryos at a second temperature, wherein the step of removing defects and the embryos is conducted in a way of thermally annealing the silicon wafer at a third temperature higher than the first temperature, and wherein the thermal annealing executed at the first temperature and the thermal annealing executed at the second temperature are conducted for 1 to several ten seconds, respectively.
2. The method for manufacturing a silicon wafer according to claim 1 , wherein the first temperature is in the range of 1,100 to 1,200° C.
3. The method for manufacturing a silicon wafer according to claim 1 , wherein the step of generating the embryos is conducted under Ar gas and/or NH3 gas atmosphere.
4. The method for manufacturing a silicon wafer according to claim 1 , wherein the silicon wafer includes substantially no impurity other than oxygen, and wherein the second temperature is in the range of 600 to 900° C.
5. The method for manufacturing a silicon wafer according to claim 1 , wherein the silicon wafer includes boron as impurity other than oxygen, and wherein the second temperature is in the range of 400 to 800° C.
6. The method for manufacturing a silicon wafer according to claim 1 , wherein the silicon wafer includes nitrogen as impurity other than oxygen, and wherein the second temperature is in the range of 600 to 1,000° C.
7. The method for manufacturing a silicon wafer according to claim 1 , wherein the silicon wafer is a silicon wafer in a vacancy-rich region, and wherein the second temperature is in the range of 1,100 to 1,300° C.
8. The method for manufacturing a silicon wafer according to claim 1 , wherein the thermal annealing executed at the third temperature is conducted for 1 to several ten seconds.
9. The method for manufacturing a silicon wafer according to claim 8 , wherein the third temperature is in the range of 1,200 to 1,300° C.
10. The method for manufacturing a silicon wafer according to claim 1 , wherein the silicon wafer has a diameter of 12 inch or more.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 27, 2007
October 30, 2012
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