A multilayer module comprised of stacked IC package layers is disclosed. A plurality of layers preferably having ball grid array I/O are stacked and interconnected using one or more interposer layers for the routing of electronic signals to appropriate locations in the module through angularly depending leads. The stack is further comprised of an interface PCB for the routing of electronics signals to and from the layers in the module and for connection to an external circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic module comprising: a first integrated circuit (IC) package layer including a first input/output (I/O) pad; an interposer layer including a lead that comprises a terminal configured to route an electrical signal to the first I/O pad; a second IC package layer including a second I/O pad; and an interface printed circuit board (PCB) including: a plurality of third I/O pads; and a plurality of interface PCB conductive traces configured to route electrical signals among the first, second, and plurality of third I/O pads, wherein one of the plurality of interface PCB conductive traces terminates at or is adjacent to a peripheral surface of the interface PCB to define an interface PCB connection point; wherein the first IC package layer, the interposer layer, the second IC package layer, and the interface PCB are arranged to form a stack; and wherein the lead is angularly disposed with respect to the interposer layer to couple to the interface PCB connection point and extends beyond an outermost surface of the interposer layer and an outermost surface of the second IC package layer such that an angularly disposed portion of the lead is spaced a distance from the outermost surface of the interposer layer and an outermost surface of the second IC package layer, and wherein the outermost surface of the interposer layer runs along a side surface of the stack.
2. The electronic module of claim 1 , wherein the interface PCB connection point comprises a castellation connection point located on a peripheral edge of the interface PCB and coupled to a terminal of the lead to form an electrical connection.
3. The electronic module of claim 2 , wherein the lead is disposed substantially perpendicular to the interposer layer.
4. The electronic module of claim 2 , further comprising a thermal management layer disposed between the first and second IC package layers,
5. The electronic module of claim 4 , wherein the thermal management layer comprises a thermally-conductive adhesive.
6. The electronic module of claim 5 , wherein the first and second IC package layers comprise at least one of a flip-chip bonded IC chip, a TSOP package, or a ball grid array package.
7. The electronic module of claim 2 , wherein the interposer layer is disposed between the first and second IC package layers, wherein one of the first or second IC package layers is disposed adjacent to the interface PCB, and wherein the terminal of the lead bypasses an edge of the one of the first or second IC package layers that is adjacent to the interface PCB and engages the castellation connection point.
8. The electronic module of claim 1 , wherein the interface PCB connection point comprises a metalized T-connect defined by a cross-section of one of the plurality of interface PCB conductive traces.
9. An electronic module comprising: a first integrated circuit (IC) package layer including a first plurality of input/output (I/O) pads; an interposer layer including: a plurality of interposer conductive pads; and a plurality of leads, each lead comprising a terminal, wherein the plurality of leads are disposed at an angle with respect to the interposer layer; wherein one of the plurality of interposer conductive pads is electrically connected to one of the first plurality of I/O pads and one of the terminals and is configured to route an electrical signal therebetween, a second IC package layer including a second plurality of I/O pads; and an interface printed circuit board (PCB) including: a plurality of interface PCB conductive pads; a third plurality of I/O pads; and a plurality of interface PCB connection points; wherein one of the plurality of interface PCB connection points is electrically connected to one of the terminals and configured to route an electrical signal to one of the first plurality of pads; wherein the interface PCB further includes a plurality of interface PCB conductive traces configured to route electrical signals from the third plurality of I/O pads to predefined ones of the terminals and predefined ones of the second plurality of I/O pads; wherein the interposer layer further includes: a first surface facing at least one of the first IC package layer, the second IC package layer, or the interface PCB; and a second surface that is substantially perpendicular to the first surface; and wherein the plurality of leads extend beyond an outermost portion of the second surface of the interposer layer and an outermost surface of the second IC package layer such that an angularly disposed portion of each of the plurality of leads is spaced a distance from the outermost portion of the second surface of the interposer layer and an outermost surface of the second IC package layer.
10. The electronic module of claim 9 , wherein the one of the plurality of interface PCB connection points comprises a castellation connection point located on a peripheral edge of the interface PCB and configured to couple to one of the terminals to form an electrical connection.
11. The electronic module of claim 10 , wherein one of first or second IC package layers comprises a flip-chip bonded IC chip, a TSOP package, or a ball grid array package.
12. The electronic module of claim 10 , wherein each of the first and second IC package layers comprises a ball grid array package.
13. The electronic module of claim 10 , further comprising a thermally-conductive adhesive configured as a thermal management layer disposed between the first and second IC package layers.
14. The electronic module of claim 10 , wherein the interposer layer is disposed between the first and second IC package layers, wherein one of the first or second IC package layers is disposed adjacent to the interface PCB, and wherein one of the terminals bypasses an edge of the one of the first or second IC package layers that is adjacent to the interface PCB and engages the castellation connection point.
15. The electronic module of claim 9 , wherein the one of the plurality of interface PCB connection points comprises one of a plated through-hole via, a plated castellation, a conductive pad, or a metalized T-connect defined by a cross-section of one of the plurality of interface PCB conductive traces.
16. A system comprising: a plurality of integrated circuit (IC) package layers, each IC package layer including a plurality of input/output (I/O) pads; an interposer layer disposed between two of the plurality of IC package layers, wherein the interposer layer includes: a plurality of interposer conductive pads; and a plurality of leads, each lead comprising a terminal, wherein the plurality of leads are disposed at an angle with respect to the interposer layer; wherein one of the plurality of interposer conductive pads is electrically connected to one of the plurality of I/O pads and one of the terminals and is configured to route an electrical signal therebetween; and an interface printed circuit board (PCB) including: a plurality of interface PCB conductive pads; and a connection point located on a peripheral surface of the interface PCB; wherein the connection point is electrically connected to one of the terminals and configured to route an electrical signal to one of the plurality of I/O pads; wherein the interface PCB further includes a plurality of interface PCB conductive traces configured to route electrical signals among the plurality of I/O pads and the terminals; wherein the first IC package layer, the interposer layer, the second IC package layer, and the interface PCB are arranged to form a stack; and wherein the plurality of leads extend beyond an outermost surface of the interposer layer and an outermost surface of the second IC package layer such that an angularly disposed portion of each of the plurality of leads is spaced a distance from the outermost surface of the interposer layer and an outermost surface of the second IC package layer, and wherein the outermost surface of the interposer layer runs along a side surface of the stack.
17. The system of claim 16 , wherein one of the plurality of leads has sufficient length and is disposed substantially perpendicular to the interposer layer to engage the castellation connection point to form an electrical connection.
18. The system of claim 16 , wherein one of the plurality of IC package layers comprises a flip-chip bonded IC chip, a TSOP package, or a ball grid array package.
19. The system of claim 16 , wherein the castellation connection point is on a peripheral edge of the interface PCB.
20. The system of claim 16 , further comprising a thermally-conductive adhesive configured as a thermal management layer disposed between the two of the plurality of IC package layers.
21. The electronic module of claim 1 , wherein the lead further comprises a single unitary element including a first portion that extends substantially parallel to a plane of the interposer layer and a second portion that is angularly disposed with respect to the plane of the interposer layer to couple to the interface PCB connection point.
22. The electronic module of claim 21 , wherein the second portion of the lead extends beyond the outermost surface of the interposer layer and the outermost surface of the second IC package layer such that a space is located between an innermost surface of the second portion of the lead and the outermost surface of the interposer layer and the outermost surface of the second IC package layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 29, 2010
October 30, 2012
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