Digital transceiver

1. A digital up-converter usable in a radio communications system for transmitting digital base-band signals to up-convert an incoming digital base-band signal into a digital band-pass signal, the digital base-band signal comprising an in-phase component and a quadrature component, comprising: at least two over-sampling units each comprising a plurality of FIR low-pass filters connected to a sample and hold circuit to over-sample the incoming in-phase component and the incoming quadrature component at an over-sampling ratio of 1/2NT, wherein 1/2NT is an arbitrary integer; at least two time-discrete sigma-delta low-pass modulators connected to the over-sampling units to convert the over-sampled in-phase component and the over-sampled quadrature component into a single bit/1.5 bit format which is a bi-serial signal representing three levels as a parallel set of a zero-bit signal and a sign-bit signal, wherein the at least two time-discrete sigma-delta low-pass modulators are resized as systolic arrays; at least one quadrature modulation unit for performing quadrature modulations to convert the incoming in-phase component and the incoming quadrature component in single/1.5 bit format into a digital band-pass signal available in single bit format or 1.5 bit format at a output of the digital up-converter.

2. The digital up-converter according to claim 1 , wherein the quadrature modulation is performed by 2:1 multiplexing and cyclic negation of the in-phase component and the quadrature component in single/1.5 bit format.

3. The digital up-converter according to claim 1 , further comprising at least two SerDes Decoder and Buffer stages to receive the in-phase component and the quadrature component via at least two serial links in a packet data frame format, to convert said in-phase component and quadrature component into at least two parallel synchronous data streams each in a same parallel data format for further processing, and to provide the two parallel synchronous data streams to said at least two over-sampling units.

4. The digital up-converter according to claim 1 , further comprising: at least one SerDes Decoder and frame buffer plus de-multiplexer stage to receive via at least one serial link, the in-phase component and the quadrature component being interlaced in a packet data frame format and further to de-multiplex, said in-phase component and said quadrature component into at least two parallel synchronous data streams each in a same parallel data format for further processing, and to provide the two parallel synchronous data streams to said at least two over-sampling units.

5. The digital up-converter according to claim 1 , wherein the at least one quadrature modulation unit performs quadrature modulation by 2:1 multiplexing and cyclic negation is realized in a pipelined structure by using only 2:1 multiplexers, logic AND and EXOR gates, and flip-flops.

6. The digital up-converter according to claim 1 , wherein the digital up-converter utilizes a multi-bit format of the digital band-pass signal.

7. The digital up-converter according to claim 1 , wherein the digital up-converter is monolithically micro-electronically integrated or integrated as a multi-chip module.

8. A computer program product embodied on a non-transitory computer-readable medium and comprising executable instructions to up-convert a digital signal using of the digital up-converter of claim 1 .

9. The digital up-converter according to claim 3 , wherein the digital up-converter utilizes as parallel data format a 16 bit format.