A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A shift register circuit comprising: an input terminal; an output terminal; a clock terminal; a first transistor for charging said output terminal by providing a constant first power supply potential to said output terminal; and a pull-up driving circuit for driving said first transistor; wherein said pull-up driving circuit includes: a second transistor for charging a first node by providing a second power supply potential larger in absolute value than the first power supply potential to said first node connected to a control electrode of said first transistor; a third transistor for providing a clock signal provided at said clock terminal to a second node connected to a control node of said second transistor; and a boosting circuit for boosting said second node, wherein a control electrode of said third transistor is charged when an input signal input to said input terminal is activated, and the control electrode of said third transistor is discharged when said second node is charged by activation of the clock signal, and wherein said boosting circuit increases the potential at said second node after the control electrode of said third transistor is discharged.
2. The shift register circuit according to claim 1 further including a fifth transistor providing the clock signal to said first node and having a control electrode connected to the control electrode of said third transistor.
3. The shift register circuit according to claim 1 , wherein said boosting circuit includes a first capacitive element whose one end is connected to said second node, and increases the potential at said second node by charging a third node connected to the other end of said first capacitive element.
4. The shift register circuit according to claim 3 , wherein said boosting circuit charges said third node by providing the second power supply potential to said third node.
5. The shift register circuit according to claim 3 , wherein said boosting circuit includes a bootstrap circuit containing a load transistor for charging said third node and having a control electrode connected to said second node, and a potential at the control electrode of said load transistor is increased by said first capacitive element in accordance with charging of said third node.
6. The shift register circuit according to claim 3 , wherein said boosting circuit includes a bootstrap circuit containing a load transistor for charging said third node and a second capacitive element connected between a control electrode of said load transistor and said third node, and a potential at the control electrode of said load transistor is increased by said second capacitive element in accordance with charging of said third node.
7. The shift register circuit according to claim 1 further comprising a fourth transistor for discharging said output terminal when a reset signal input to a predetermined reset terminal is activated.
8. The shift register circuit according to claim 7 further comprising: a fifth transistor for discharging said output terminal; and a pull-down driving circuit for driving the fifth transistor, wherein said pull-down driving circuit discharges a control electrode of said fifth transistor when the input signal is activated, and charges the control electrode of said fifth transistor when the reset signal is activated.
9. The shift register circuit according to claim 1 further comprising a fourth transistor for discharging said output terminal, wherein another clock signal having a phase different from the clock signal input to said clock terminal is provided to a control electrode of said fourth transistor during at least an activated period of an output signal output from said output terminal.
10. The shift register circuit according to claim 9 further comprising: a fifth transistor for discharging said output terminal; and a pull-down driving circuit for driving the fifth transistor, wherein said pull-down driving circuit discharges a control electrode of said fifth transistor when the input signal is activated, and discharges the control electrode of said fifth transistor when a signal provided to the control electrode of said fourth transistor is activated.
11. The shift register circuit according to claim 1 , wherein said pull-up driving circuit further includes a sixth transistor connected between said first node and said clock terminal and having a control electrode connected to said output terminal.
12. The shift register circuit according to claim 1 , further including a seventh transistor connected between said output terminal and said clock terminal and having a control electrode connected to said input terminal.
13. A multiple-stage shift register circuit including a plurality of cascade-connected shift register circuits, wherein each stage of said multiple-stage shift register circuit is the shift register circuit according to claim 1 , and further comprises a switching circuit receiving an output signal from a preceding stage and an output signal from a subsequent stage and capable of switching which of the output signal received from said preceding stage and the output signal received from said subsequent stage is provided to said input terminal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 23, 2012
October 30, 2012
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