Low-temperature wafer bonding of semiconductors to metals

1. A method of bonding together a metal substrate and a semiconductor substrate without the use of any intermediate joining layer between the two substrates, the method comprising the steps of: polishing a surface of the metal substrate and a surface of the semiconductor substrate so that each surface has a predetermined level of smoothness and a predetermined level of flatness, cleaning the surface of the metal substrate and the surface of the semiconductor substrate so as to remove from each surface particulates of a predetermined size, contaminants and residues, bonding together the metal substrate and the semiconductor substrate by contacting the surface of the metal substrate with the surface of the semiconductor substrate.

2. The method of claim 1 further comprising a step of activating the surfaces of the semiconductor and metal substrate prior to physically contacting the surfaces of the substrates.

3. The method of claim 1 further comprising a step of applying a force to the surfaces of the semiconductor and metal substrates during the step of physically contacting the surfaces of the substrates or after the surfaces of the substrates have been physically contacted.

4. The method of claim 1 further comprising a step of annealing the semiconductor and metal substrates for a predetermined period of time and a predetermined elevated temperature to thereby bond the metal substrate and the semiconductor substrate together.

5. The method of claim 1 , wherein the predetermined surface smoothness is substantially between two and five Angstroms.

6. The method of claim 1 , wherein the predetermined surface smoothness corresponds to a Root-Means-Square (“RMS”) surface roughness substantially between 0.5 Angstroms and a several nanometers RMS.

7. The method of claim 1 , wherein the step of cleaning the surfaces of the metal and semiconductor substrates is performed by immersing of the metal and semiconductor substrates in a chemical cleaning solution.

8. The method of claim 7 , wherein the step of cleaning the semiconductor and metal substrates is followed by the steps of subsequently rinsing the substrates in de-ionized water, followed by spin-rinsing and drying the substrates before physically contacting the substrate surfaces.

9. The method of claim 1 , wherein the metal substrate and the semiconductor substrate each have markings on them to allow them to be aligned prior to being bonded together.

10. The method of claim 1 , wherein the surface of the metal substrate and the surface of the semiconductor substrate are polished using a chemical-mechanical polishing process.

11. The method of claim 1 , wherein the predetermined surface flatness is a surface variation between approximately one to two microns over a substrate area having a diameter of 100 mm or less.

12. The method of claim 1 , wherein the step of bonding together the metal substrate and the semiconductor substrate by contacting the surface of the metal substrate with the surface of the semiconductor substrate is performed in a clean environment that is equivalent to a class-10 or better.

13. The method of claim 1 , wherein the predetermined surface flatness of the surface of the metal substrate and the surface of the semiconductor substrate is further achieved using planarization of the metal substrate and semiconductor substrate surfaces.

14. The method of claim 10 , wherein the slurry used in the chemical-mechanical polishing process is selected according to the types of semiconductor and metal substrates to be bonded together.

15. The method of claim 7 , wherein the step of cleaning the surfaces of the metal and semiconductor substrates is performed using a combination of slightly acidic and/or slightly basic solutions combined with physical agitation of the metal and semiconductor substrates.

16. The method of claim 7 , wherein the step of cleaning the surfaces of the metal and semiconductor substrates is performed using a solvent solution combined with physical agitation of the metal and semiconductor substrates.

17. The method of claim 7 , wherein the step of cleaning the surfaces of the metal and semiconductor substrates further comprises softly brushing the surfaces of the metal and semiconductor substrates without damaging, etching, or roughening said surfaces.

18. The method of claim 7 , wherein the step of cleaning the surfaces of the metal and semiconductor substrates further comprises subjecting said substrate surfaces to ultrasonic agitation during the chemical immersion of said substrates without degrading the smoothness of said substrate surfaces.

19. The method of claim 7 , wherein the step of cleaning the surfaces of the metal and semiconductor substrates further comprises removing organic residues using a chemical-cleaning agent comprised of a mixture of five parts of de-ionized water to one part each of ammonium hydroxide and hydrogen peroxide.

20. The method of claim 7 , wherein the step of cleaning the surfaces of the metal and semiconductor substrates further comprises heating the chemical-cleaning agent to a temperature between 25° C. and 100° C., immersing the metal and semiconductor substrates in the chemical-cleaning agent for approximately 15 minutes, rinsing the metal and semiconductor substrates in de-ionized water, spin-rinsing and then drying the metal and semiconductor substrates before performing the step of contacting the surfaces of the metal and semiconductor substrates.

21. The method of claim 7 , wherein the step of cleaning the surfaces of the metal and semiconductor substrates further comprises immersing the metal and semiconductor substrates in a mixture comprised of three parts of sulfuric acid to one part of hydrogen peroxide.

22. The method of claim 21 , wherein the step of cleaning the surfaces of the metal and semiconductor substrates further comprises immersing the metal and semiconductor substrates in the acidic mixture for approximately five to fifteen minutes after the mixture forms an exothermic reaction that self-heats up to between 80° C. and 100° C., subsequently rinsing the metal and semiconductor substrates in de-ionized water and then spin-rinsing and drying the metal and semiconductor substrates before performing the step of contacting the surfaces of the metal and semiconductor substrates.

23. The method of claim 2 , wherein the step of activating the surfaces of the metal and semiconductor substrates further comprises terminating molecular bonds at the surfaces of the metal and semiconductor substrates dipole molecules so as to increase the bonding strength due to strong dipole-to-dipole attractions across an interface between the surfaces of the metal and semiconductor substrates.

24. The method of claim 4 , wherein the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature of at least approximately 200° C. for approximately an hour.

25. The method of claim 4 , wherein the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature of at least approximately 400° C. for approximately an hour.

26. The method of claim 4 , wherein the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature of at least approximately 600° C. for approximately an hour.

27. The method of claim 4 , wherein the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature of at least approximately 800° C. for approximately an hour.

28. The method of claim 4 , wherein the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature of at least approximately 1,000° C. for approximately an hour.

29. The method of claim 2 , wherein the step of activating the surfaces of the semiconductor and metal substrates to be bonded is performed using wet chemical immersion, exposure to a plasma field, exposure to a laser beam, and/or exposure to an energy source that results in charges being placed onto the surfaces of the substrates.

30. The method of claim 2 , wherein the step of activating the surfaces of the semiconductor and metal substrates to be bonded is comprised of exposing the surfaces of the metal and semiconductor substrates to an oxygen plasma, after cleaning and before bonding said surfaces, and wherein the metal and semiconductor substrates are then annealed at a temperature of approximately 400° C. or lower.

31. The method of claim 2 , wherein the step of activating the surfaces of the semiconductor and metal substrates to be bonded is comprised of exposing the surfaces of the metal and semiconductor substrates, after cleaning and before bonding, to an oxygen plasma, and wherein the metal and semiconductor substrates are then annealed at a temperature of approximately 200° C. or lower.

32. The method of claim 2 , wherein the step of activating the surfaces of the semiconductor and metal substrates to be bonded is comprised of exposing the two substrates, after cleaning and before bonding, to a plasma selected from the group consisting of oxygen, nitrogen and ammonia.

33. The method of claim 1 , further comprising the step of applying an electrical potential field across the metal and semiconductor substrates after the substrates have been bonded and during the annealing step.

34. The method of claim 2 , wherein the step of activating the surfaces of the semiconductor and metal substrates to be bonded is comprised of applying an electrical charge on one or both of the surfaces of the semiconductor and metal substrates.

35. The method of claim 10 , wherein the surface of the metal substrate and the surface of the semiconductor substrate are polished using the chemical-mechanical polishing process in which a slurry composed of abrasives immersed in a chemical etchant solution is applied to the metal and semiconductor substrate surfaces as said surfaces are forced under pressure loading against moving polishing pads.

36. The method of claim 2 , wherein the step of activating the surfaces of the semiconductor and metal substrates is comprised of applying an electrical potential field across the metal and semiconductor substrates, and wherein the step of applying the electrical potential field is comprised of placing the substrates on a heating element, applying a force to the substrates and applying the electrodes to the metal and semiconductor substrates to create a voltage potential across said substrates.

37. The method of claim 1 , further comprising the step of applying an electrical potential field across the metal and semiconductor substrates after the substrates have been bonded, and wherein the annealing step is not performed.

38. The method of claim 1 further comprising the step of removing from each of the metal and semiconductor substrates native oxides on the surfaces of said substrates to thereby produce a low resistance electrical conduction through an interface between the surfaces of the semiconductor and metal substrates.

39. The method of claim 38 further comprising the step of removing from each of the metal and semiconductor substrates native oxides on the surfaces of said substrates that are at least approximately several Angstroms to approximately several nanometers in thickness.

40. The method of claim 39 , wherein the step of removing the native oxides, where the semiconductor substrate is silicon, is comprised of immersing, for less than approximately one minute, the silicon substrate in a solution composed of a dilute hydrofluoric acid in water with a concentration ranging between approximately 10:1 and approximately 50:1.

41. The method of claim 39 , wherein the step of removing the native oxides, where the metal substrate is copper or a mixture of predominantly copper and another metal, is comprised of immersing, for several minutes at a temperature of approximately 35° C., the metal substrate in a solution comprised of acetic acid having a concentration of up to 4 vol % water dilution.

42. The method of claim 39 , wherein the step of removing the native oxides, where the semiconductor substrate is Gallium Arsenide, is comprised of immersing, for several minutes, the semiconductor substrate in a solution comprised of a ratio of one part NH 4 OH to 10 to 20 parts H 2 O.

43. The method of claim 8 , further comprising the step of drying the semiconductor and metal substrates by blowing an inert gas across the surfaces of the semiconductor and metal substrates to thereby remove any liquid from said surfaces or by placing the semiconductor and metal substrates in a vacuum to thereby evaporate any remaining liquids from said surfaces.

44. The method of claim 8 , wherein the method further comprises the step of contacting the surfaces of the semiconductor and metal substrates in the presence of an ambient gas to enclose the gas inside any cavities present in the bonded substrates.

45. The method of claim 43 , wherein the inert gases are Argon or Nitrogen.

46. The method of claim 44 further comprising the step of contacting the surfaces of the semiconductor and metal substrates in the presence of a vacuum to create a sealed vacuum inside any cavities present in the bonded substrates.

47. The method of claim 29 , wherein the method further comprises annealing the bonded substrates in a non-oxidizing ambient gas at an annealing temperature of at least approximately 100° C. for an annealing time of at least approximately 15 minutes.

48. The method of claim 1 , wherein the step of joining together the metal substrate and the semiconductor substrate by contacting the surface of the metal substrate with the surface of the semiconductor substrate is performed in a clean environment that is equivalent to a class-100 clean room or better.

49. The method of claim 1 , wherein the step of joining together the metal substrate and the semiconductor substrate by contacting the surface of the metal substrate with the surface of the semiconductor substrate is performed in a clean environment that is equivalent to a class-10 clean room or better.

50. The method of claim 1 , wherein the step of joining together the metal substrate and the semiconductor substrate by contacting the surface of the metal substrate with the surface of the semiconductor substrate is performed in a clean environment that is equivalent to a class-1 clean room or better.

51. The method of claim 47 , wherein the non-oxidizing ambient gas is Nitrogen or Argon.

52. The method of claim 2 , wherein the step of activating the surfaces of the metal and semiconductor substrates comprises subjecting said surfaces to a plasma treatment.

53. The method of claim 52 , wherein the step of subjecting the metal and semiconductor substrate surfaces to a plasma treatment comprises inserting the metal and semiconductor substrates, after they have been cleaned, into a vacuum chamber having a pressure between approximately 50 mTorr and 250 mTorr, striking a plasma in the chamber using either Nitrogen (N2), Ammonia (NH3), Oxygen (O2), or a combination thereof, and exposing the surfaces of the metal and semiconductor substrates to the plasma for a period of time of approximately less than 1 minute to approximately less than 10 minutes, removing the substrates from the vacuum chamber, whereupon the step of physically contacting the surface of the metal substrate with the surface of the semiconductor substrate is immediately performed, and then the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature between approximately 35° C. and approximately 400° C.

54. The method of claim 2 , wherein the step of activating the surfaces of the metal and semiconductor substrates involves immersing the substrates in a de-ionized water or aqueous solution, to thereby allow free radicals to attach to the surfaces and thereby enhance the bonding between the surface of the metal substrate and the surface of the semiconductor substrate, removing the substrates from the solution, rinsing them in Deionized water, followed by a spin rinse and dry, whereupon the step of physically contacting the surface of the metal substrate with the surface of the semiconductor substrate is immediately performed, and then the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature between approximately 35° C. and approximately 400° C.

55. The method of claim 52 , wherein the step of subjecting the metal and semiconductor substrate surfaces to a plasma treatment comprises inserting the wafers, after they have been cleaned, into a vacuum chamber with an inside pressure between 2 mTorr and 8 mTorr, striking a plasma in the chamber using a Hydrogen plasma in a ration of approximately 1:1 with Argon, exposing the surfaces of the substrates to the plasma for a period of time between several seconds and 15 minutes, and, without breaking vacuum, taking the substrates to an Ultra-High Vacuum pressure and 600° C. for approximately 2 to 6 minutes to thereby remove hydrogen on the surfaces to leave clean, reactive and hydrophilic surfaces, whereupon the step of physically contacting the surface of the metal substrate with the surface of the semiconductor substrate is immediately performed, and then the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature between approximately 35° C. and approximately 400° C.

56. The method of claim 55 , wherein the Ultra-High Vacuum pressure is between approximately 10 −7 Pascals and approximately 10 −10 Pascals.

57. The method of claim 52 , wherein the step of subjecting the metal and semiconductor substrate surfaces to a plasma treatment comprises placing the substrates in an Ultra-High Vacuum pressure chamber and heating them to approximately 850 degrees Celsius for approximately 20 to 40 minutes at a pressure of approximately 10 −9 to 10 −10 Pascals, whereupon the step of physically contacting the surface of the metal substrate with the surface of the semiconductor substrate is immediately performed, and then the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature between approximately 35° C. and approximately 400° C.

58. The method of claim 2 , wherein the metal and semiconductor substrate surface cleaning, activating and contacting steps are performed in an Ultra-High Vacuum pressure chamber.

59. The method of claim 4 , wherein the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature of at least approximately 50° C. to produce a low resistance electrical conductance across an interface between the contacted surfaces of the metal and semiconductor substrates.

60. The method of claim 4 , wherein the step of contacting the surface of the metal substrate with the surface of the semiconductor substrate is performed in an Ultra-High Vacuum pressure chamber, and wherein the metal and semiconductor substrates are heated to a temperature of at least approximately 100° C. to produce a low resistance electrical conductance across an interface between the contacted surfaces of the metal and semiconductor substrates.

61. The method of claim 2 , further comprising the step of doping the surface of the semiconductor substrate with Boron using either diffusion or ion implantation prior to the cleaning and activating steps being performed to produce a low resistance electrical conductance across an interface between the contacted surfaces of the metal and semiconductor substrates.

62. The method of claim 1 , further comprising the steps of depositing a thin film layer of transition metal on the surface of the semiconductor substrate, physically contacting and pressing together the semiconductor and metal substrates using a moderate amount of normal pressure to pre-bond the substrates, and then annealing the pre-bonded substrates at a temperature of between 50° C. and 400° C. to complete the bonding of the semiconductor and metal substrates and thereby produce a low resistance electrical conductance across an interface between the contacted surfaces of the metal substrate and the semiconductor substrate.

63. The method of claim 62 , further comprising the steps of cleaning and preparing the semiconductor and metal substrates prior to physically contacting and pressing the substrates together.

64. The method of claim 63 , further comprising the steps of cleaning and preparing the semiconductor and metal substrates by immersing said substrates in a cleaning solution.

65. The method of claim 64 , wherein the cleaning solution is a weak acidic solution containing either Acetic acid, Hydrochloric acid, Nitric acid, or a mixture of these acids, and wherein the normal pressure is several PSI.

66. The method of claim 64 , wherein the cleaning solution for the semiconductor substrate is comprised of a ratio of one part NH 4 OH to 10 to 20 parts H 2 O.

67. The method of claim 62 , wherein the transition metal is selected from the group consisting of Palladium, Cobalt, Nickel, Copper, Rhodium, Silver, Iridium, Platinum, Gold and any combination of these metals.

68. The method of claim 1 , further comprising the step of degenerately doping the surface of the semiconductor substrate to thereby produce an ohmic contact between the contacted surfaces of the metal and semiconductor substrates.

69. The method of claim 68 , further comprising the step of degenerately doping the surface of the semiconductor substrate with Boron using either diffusion or ion implementation.

70. The method of claim 68 , wherein the semiconductor substrate is an n-type substrate and wherein the method further comprises the step of degenerately doping the semiconductor substrate with an n-type dopant to thereby produce an ohmic contact between the contacted surfaces of the metal substrate and the semiconductor substrate.

71. The method of claim 68 , wherein the semiconductor substrate is a p-type substrate and wherein the method further comprises the step of degenerately doping the semiconductor substrate with a p-type dopant to thereby produce an ohmic contact between the contacted surfaces of the metal substrate and the semiconductor substrate.

72. The method of claim 1 , further comprising the step of forming a silicide at the contacted metal and semiconductor substrate surfaces by depositing a transition metal onto the surface of the semiconductor substrate and annealing the semiconductor substrate with the metal deposition to thereby produce an ohmic contact between the contacted surfaces of the metal substrate and the semiconductor substrate.

73. The method of claim 72 , wherein the semiconductor substrate is silicon and the transition metal is selected to react with the silicon to form a silicide.

74. The method of claim 72 , wherein the semiconductor substrate is Gallium Arsenide and the transition metal is selected to react with the silicon to form a silicide.

75. The method of claim 72 , wherein the transition metal is selected from the group consisting of Titanium, Tungsten, Platinum, Aluminum, Aluminum-Silicon and Gold.

76. The method of claim 72 , wherein the semiconductor substrate is Germanium and the transition metal is selected from the group consisting of Indium, Gold-Gallium and Gold-Antimony.

77. The method of claim 72 , wherein the semiconductor is Gallium Arsenide and the transition metal is selected from the group consisting of Gold-Germanium, Palladium-Germanium, Titanium-Platinum-Gold deposited onto the semiconductor surface prior to bonding to thereby produce an ohmic contact between the semiconductor and metal substrates.

78. The method of claim 2 , wherein the surface activating step is comprised of scanning the semiconductor and metal surfaces with a laser immediately prior to physically contacting the semiconductor and metal surfaces.

79. The method of claim 78 , wherein the surface activating step is further comprised of scanning the semiconductor surface with a pulsed femto-second laser with a power level that heats, but does not melt, the semiconductor substrate immediately at the semiconductor surface to between approximately 500° C. and 800° C. in a period of time that is less than approximately 100 nanoseconds.

80. The method of claim 79 , wherein the laser scanning of the semiconductor surface is performed in a vacuum environment.

81. The method of claim 78 , wherein the laser is a gas laser or solid state laser with a wave length extending from infrared to near ultraviolet.

82. The method of claim 78 , wherein the semiconductor and metal substrates are physically contacted and annealed after the substrates have been scanned with the femto-second laser.

83. The method of claim 78 , wherein the semiconductor and metal substrates are immersed in a solution to allow activation of the surfaces with molecular species after the substrates have been scanned with the femto-second laser.

84. The method of claim 1 , wherein the semiconductor and metal substrates are placed in a microwave chamber after being physically contacted and then irradiated with a microwave beam directed at an interface between the semiconductor and metal surfaces from the side of the semiconductor substrate so as to heat an interface between the semiconductor and metal substrates.

85. The method of claim 84 , wherein the microwave chamber is evacuated.

86. The method of claim 84 , wherein the microwave chamber is filled with a non-reactive gas.

87. The method of claim 84 , wherein the semiconductor and metal surfaces are activated using plasma activation or laser activation prior to physically contacting the semiconductor and metal surfaces and irradiating them with the microwave beam.

88. The method of claim 84 , wherein the semiconductor surface has Boron diffused or implanted into the semiconductor surface prior to physically contacting the semiconductor surface and the metal surface and irradiating said surfaces with the microwave beam.

89. The method of claim 84 , wherein a layer of reactive metal is deposited on the semiconductor surface prior to physically contacting the semiconductor surface and the metal surface and irradiating the two surfaces with the microwave beam.

90. The method of claim 84 , wherein a layer of transitional metal is deposited on the semiconductor surface and annealed to form a silicide on the surface prior to physically contacting the semiconductor surface and the metal surface and irradiating the two surfaces with the microwave beam.

91. The method of claim 84 , wherein the semiconductor surface is degenerately doped with a dopant selected according to the type of semiconductor material and annealed prior to physically contacting the semiconductor surface and the metal surface and irradiating the two surfaces with the microwave beam.

92. The method of claim 1 , wherein the predetermined particulates size is particulates being sub-micron in diameter.

93. A method of bonding together a Gallium Arsenide semiconductor substrate to a metal substrate that functions as a heat sink and as an electrode to supply current to active devices in the Gallium Arsenide semiconductor without the use of any intermediate joining layer between the two substrates, the method comprising the steps of: lapping and polishing a surface of the semiconductor substrate and a surface of the metal substrate so that each surface has a predetermined level of smoothness and a predetermined level of flatness, cleaning the surfaces of the semiconductor and metal substrates using suitable solutions for the semiconductor and metal substrates so as to remove from the surfaces of the semiconductor and metal substrates particulates of a predetermined size, contaminants and residues, removing from the surfaces of the semiconductor and metal substrates any native oxides using appropriate solutions for the semiconductor and metal substrates, drying the surfaces of the semiconductor and metal substrates and pre-bonding said surfaces together by physically contacting said surfaces together, and annealing the semiconductor and metal substrates for a predetermined period of time and a predetermined elevated temperature to thereby bond the semiconductor and metal substrates together.

94. The method of claim 93 , wherein the step of cleaning the surfaces of the semiconductor and metal substrates comprises the steps of immersing the semiconductor and metal substrates in trichloroethane 1,1,1 for a first period of time between approximately five minutes and approximately 15 minutes, immersing the semiconductor and metal substrates in acetone for a second period of time between approximately five minutes and approximately 15 minutes, immersing the semiconductor and metal substrates in methanol for approximately five minutes and approximately 15 minutes, and immersing the semiconductor and metal substrates in isopropanol for approximately five minutes and approximately 15 minutes.

95. The method of claim 94 , wherein solutions used to clean the semiconductor and metal substrates are heated to the boiling point of the respective solutions.

96. The method of claim 93 , wherein the step of removing the native oxides comprises the step of immersing the semiconductor substrate in a solution having a mixture of NH4OH and H2O.

97. The method of claim 96 , wherein the solution to cleaning the surfaces and remove the native oxide is a mixture of NH4OH and H2O in a proportion between approximately 10:1 and approximately 20:1 for a period of time between approximately 1 minute and approximately 5 minutes under agitation or irrigation.

98. The method of claim 93 , wherein the step of cleaning the surfaces and removing the native oxides comprises the step of immersing the semiconductor substrate in a dilute acidic solution having a mixture of HCl and H2O in a proportion of approximately 1:1.

99. The method of claim 93 , wherein the step of cleaning the surfaces and removing the native oxides comprises the step of immersing the semiconductor substrate in a dilute acidic solution having a mixture of H3PO4 and H2O in a proportion of approximately 1:1.

100. The method of claim 93 , wherein the metal substrate has the native oxides removed from the surface by immersing the metal substrate in a solution of acetic acid (CH3COOH) at a concentration of approximately 4 vol % water dilution or less at 35° C. for approximately several minutes.

101. The method of claim 93 , wherein the metal substrate is Copper or has a proportion of its composition made from Copper.

102. The method of claim 93 , wherein the semiconductor and metal substrates are subjected to ultrasonic agitation for one or more of the immersion steps.

103. The method of claim 93 , wherein the step of drying the surfaces of the semiconductor and metal substrates comprises blowing an inert gas across said surfaces to remove any liquid on said surfaces.

104. The method of claim 93 , wherein the step of drying the surfaces of the semiconductor and metal substrates comprises placing the substrates in a vacuum to evaporate any liquids on the surfaces of the substrates.

105. The method of claim 93 , wherein the step of pre-bonding the semiconductor and metal substrate surfaces together further comprises compressing the semiconductor and metal substrates together after physically contacting said substrates together.

106. The method of claim 93 , wherein the predetermined period of time is approximately at least 5 minutes and wherein the predetermined elevated temperature is approximately at least 50° C.

107. The method of claim 106 , wherein the step of annealing the semiconductor and metal substrates is performed in a non-oxidizing ambient gas that is Nitrogen or Argon.

108. The method of claim 93 , further comprising the step of activating the surfaces of the semiconductor and metal substrates using plasma activation prior to physically contacting and annealing the semiconductor and metal substrate surfaces.

109. The method of claim 93 , further comprising the step of activating the surfaces of the semiconductor and metal substrates using laser activation prior to physically contacting and annealing the semiconductor and metal substrate surfaces.

110. The method of claim 93 , wherein Boron is diffused or implanted into the surface of the semiconductor substrate prior to physically contacting and annealing the semiconductor and metal substrate surfaces.

111. The method of claim 93 , wherein Palladium or Gold or a combination of the two is deposited as a thin layer on the surface of the semiconductor substrate prior to physically contacting and annealing the semiconductor and metal substrate surfaces.

112. The method of claim 93 , wherein the surface of the semiconductor substrate is degenerately doped using a dopant species appropriate for a Gallium Arsenide semiconductor prior to physically contacting and annealing the semiconductor and metal substrate surfaces.

113. The method of claim 93 , wherein a thin layer of a transition metal is deposited on the surface of the semiconductor substrate to form a silicide on the surface of the semiconductor substrate surface prior to physically contacting and annealing the semiconductor and metal substrate surfaces.

114. The method of claim 1 , wherein the semiconductor substrate is bonded to at least one second semiconductor substrate prior to bonding of the semiconductor substrate to the metal substrate.

115. The method of claim 1 , wherein the semiconductor substrate is bonded to metal substrate and then this composite bonded semiconductor to metal substrate pair is bonded to one or more additional semiconductor substrates.

116. The method of claim 1 , wherein a multiplicity of semiconductor substrates are bonded to one or more metal substrates.

117. The method of claim 1 , wherein the semiconductor substrate is bonded to second and third semiconductor substrates prior to bonding of the semiconductor substrate to the metal substrate, and wherein the semiconductor substrates include microelectronic, photonic and/or MEMS devices fabricated into them.

118. The method of claim 1 , wherein the metal substrate has a ceramic enclosure formed on it and wherein the semiconductor substrate has microelectronic, photonic and/or MEMS devices fabricated on it, and wherein the semiconductor substrate is bonded to the metal substrate within the ceramic enclosure and the ceramic enclosure is sealed to completely encapsulate the semiconductor substrate after the semiconductor substrate has been bonded to the metal substrate.

119. The method of claim 1 , wherein the metal substrate is a thin, metal layer fabricated on a second semiconductor or ceramic substrate, and wherein the semiconductor substrate includes microelectronic, photonic and/or MEMS devices fabricated into it and is bonded to the metal substrate after the metal substrate has been fabricated on the second semiconductor or ceramic substrate.

120. The method of claim 119 , wherein the metal layer functions as an active or passive heat sink to remove waste heat from the semiconductor substrate.

121. The method of claim 120 , wherein the metal heat sink to remove waste heat from the semiconductor substrate is composed of a heat pipe, a capillary pumped loop, a microchannel cooler with liquid forced through its internal passages, a spray cooler wherein liquid is sprayed against the hot surfaces, or some other single phase or two phase liquid cooling mechanism.

122. The method of claim 1 , wherein the metal substrate is a thin, metal layer fabricated on a second semiconductor substrate that includes microelectronic, photonic and/or MEMS devices fabricated into it, and wherein the metal substrate is bonded to the semiconductor substrate.

123. The method of claim 122 , wherein the metal layer functions as electrodes that enable power to be delivered to any devices on the second semiconductor substrate.

124. The method of claim 122 , wherein a ceramic substrate is substituted for the semiconductor substrate.

125. A method of bonding together a metal substrate and a semiconductor substrate without the use of any intermediate joining layer between the two substrates, the method comprising the steps of: polishing a surface of the metal substrate and a surface of the semiconductor substrate using a chemical-mechanical polishing process so that each surface has a predetermined level of smoothness and a predetermined level of flatness, cleaning the surface of the metal substrate and the surface of the semiconductor substrate using one or more appropriate cleaning solutions and physical agitation of the metal and semiconductor substrates so as to remove from each surface particulates of a predetermined size, contaminants and residues, activating the surface of the metal substrate and the surface of the semiconductor substrate by subjecting said surfaces to a plasma treatment or by scanning the said surfaces with a laser, pre-bonding together the metal substrate and the semiconductor substrate by contacting the surface of the metal substrate with the surface of the semiconductor substrate in a clean environment and applying a force to the metal substrate and the semiconductor substrate, and annealing the metal substrate and the semiconductor substrate for a predetermined period of time and a predetermined elevated temperature to thereby bond the metal substrate and the semiconductor substrate together.

126. The method of claim 125 , wherein the predetermined surface smoothness is substantially between 1 Angstroms and several nanometers.

127. The method of claim 125 , wherein the predetermined surface flatness is a surface variation between approximately one to two microns over a substrate area having a diameter of 100 mm or less.

128. The method of claim 125 , wherein the predetermined particulates size is particulates being sub-micron in diameter.

129. The method of claim 125 , wherein the step of cleaning the surface of the metal substrate and the surface of the semiconductor substrate is performed by immersing of the metal substrate and the semiconductor substrate in a chemical cleaning solution.

130. The method of claim 125 comprising further comprising the step of removing from each of the metal and semiconductor substrates native oxides on the surfaces of said substrates to thereby produce a low resistance electrical conduction through an interface between the surfaces of the semiconductor and metal substrates.

131. The method of claim 125 , wherein Boron is diffused or implanted into the surface of the semiconductor substrate prior to physically contacting and annealing the semiconductor and metal substrate surfaces to form a low electrical resistance across the bonded interface.

132. The method of claim 125 , wherein Palladium or Gold or a combination of the two is deposited on the surface of the semiconductor substrate prior to physically contacting and annealing the semiconductor and metal substrate surfaces to form a low electrical resistance across the bonded interface.

133. The method of claim 125 , wherein the surface of the semiconductor substrate is degenerately doped using a dopant species appropriate for the semiconductor substrate prior to physically contacting and annealing the semiconductor and metal substrate surfaces to form a low electrical resistance across the bonded interface.

134. The method of claim 125 , wherein a thin layer of a transition metal is deposited on the surface of the semiconductor substrate prior to physically contacting and annealing the semiconductor and metal substrate surfaces to form a low electrical resistance across the bonded interface.

135. The method of claim 125 , wherein the semiconductor substrate includes microelectronic, photonic and/or MEMS devices fabricated into it.

136. The method of claim 125 , wherein the metal substrate functions as an active or passive heat sink to remove waste heat from the semiconductor substrate.

137. The method of claim 136 , wherein the metal heat sink to remove waste heat from the semiconductor substrate is composed of a heat pipe, a capillary pumped loop, a microchannel cooler with liquid forced through its internal passages, a spray cooler wherein liquid is sprayed against the hot surfaces, or some other single phase or two phase liquid cooling mechanism.

138. The method of claim 134 , wherein the metal layer functions as electrodes that enable power to be delivered to any devices on the second semiconductor substrate.

139. The method of claim 1 , wherein the predetermined surface flatness of the surface of the metal substrate and the surface of the semiconductor substrate is further achieved using lapping of the metal substrate and/or semiconductor substrate surfaces.

140. The method of claim 1 , wherein the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature ranging from several degrees above room temperature to over 100° C.

141. The method of claim 1 further comprising exposing the bonded metal and semiconductor substrates to ultrasonic acoustical energy to bond the two substrates together at a low temperature and applied force.

142. The method of claim 1 , wherein the metal substrate is a shaped piece of material made from an elemental metal, an alloyed metal made from two or more metal types intermixed in a solid phase state, or a composite metal material made from two or more metal material types brought or pressed together to form a metal composite substrate.

143. The method of claim 4 , wherein the annealing step is performed from several degrees above room temperature to over 1000° C. for a time period between several minutes to several hours, depending on the degree that the metal and semiconductor substrate surfaces have been thoroughly smoothed, flattened, cleaned and activated.

144. The method of claim 4 , wherein the pre-bonding force is applied simultaneously while the elevated temperature anneal is being performed by the application of heat to the metal and semiconductor substrates during bonding.

145. The method of claim 3 , wherein the pre-bonding force that is applied is normal to the surfaces of the metal and/or semiconductor substrate surfaces.

146. The method of claim 3 , wherein the pre-bonding force is applied before the elevated temperature anneal is being performed by the application of heat to the metal and semiconductor substrates during bonding.

147. The method of claim 2 , wherein the surface activating step is comprised of exposing only the surface of the semiconductor substrate, after cleaning and before bonding, to an oxygen plasma.

148. The method of claim 1 , wherein a low resistance electrical conductance across an interface between the bonded semiconductor substrate and a metal substrate is obtained by depositing a thin layer of Palladium or Gold or a combination of the two on the surface of the semiconductor substrate.

149. The method of claim 148 , wherein the thin layer of Palladium or Gold or a combination of the two has a thickness between several tens and several thousand Angstroms.

150. The method of claim 1 , wherein an ohmic contact between the semiconductor and metal substrates is obtained by depositing a thin metal layer of Palladium, Gold, Gold-Germanium, Palladium-Germanium, or Titanium-Platinum-Gold onto the smaller bandgap semiconductor material prior to bonding of the metal and semiconductor substrates.

151. The method of claim 1 , wherein a thin layer of Palladium or Gold or a combination of the two is deposited on the surface of the semiconductor substrate and the metal and semiconductor substrates are then exposed to an ultrasonic acoustical energy beam.

152. The method of claim 151 , wherein the semiconductor substrate and the metal and semiconductor substrates are exposed to the ultrasonic acoustical energy beam with the simultaneous application of a normal force and, optionally, heat to the metal and semiconductor substrates to bond said substrates together.

153. A method of bonding together a metal substrate and a semiconductor substrate without the use of any intermediate joining layer between the two substrates, the method comprising the steps of: polishing a surface of the metal substrate and a surface of the semiconductor substrate so that each surface has a predetermined level of smoothness and a predetermined level of flatness, cleaning the surface of the metal substrate and the surface of the semiconductor substrate so as to remove from each surface particulates of a predetermined size, contaminants and residues, pre-bonding together the metal substrate and the semiconductor substrate by contacting the surface of the metal substrate with the surface of the semiconductor substrate, applying a force to the metal substrate and the semiconductor substrate while contacting the surface of the metal substrate with the surface of the semiconductor substrate, and annealing the metal substrate and the semiconductor substrate for a predetermined period of time and a predetermined elevated temperature to thereby bond the metal substrate and the semiconductor substrate together.

154. The method of claim 153 further comprising activating the surface of the metal substrate and the surface of the semiconductor substrate.

155. The method of claim 153 , wherein the predetermined surface flatness of the surface of the metal substrate and the surface of the semiconductor substrate is further achieved using lapping of the metal substrate and/or semiconductor substrate surfaces.

156. The method of claim 153 , wherein the predetermined surface smoothness is substantially between two and five Angstroms.

157. The method of claim 153 , wherein the predetermined surface smoothness corresponds to a Root-Means-Square (“RMS”) surface roughness substantially between 0.5 Angstroms and several nanometers RMS.

158. The method of claim 153 , wherein the predetermined surface flatness is a surface variation between approximately one to two microns over a substrate area having a diameter of 100 mm or less.

159. The method of claim 153 , wherein the predetermined particulates size is particulates being sub-micron in diameter.

160. The method of claim 153 , wherein the predetermined elevated annealing temperature is at least approximately 50° C., and wherein the predetermined period of annealing time is at least approximately 15 minutes.

161. The method of claim 4 , wherein the step of annealing the metal substrate and the semiconductor substrate is performed at a temperature of at least approximately 50° C. for approximately an hour.