A memory having a plurality of ferroelectric memory cells connected between first and second bit lines is disclosed. A read circuit is also connected between the first and second bit lines. A word select circuit selects one of the ferroelectric memory cells and generates a potential on the first hit line indicative of a value stored in the selected one of the plurality of ferroelectric memory cells. Each ferroelectric memory cell includes a ferroelectric capacitor and a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal. The ferroelectric capacitor is connected between the control terminal and the first switch terminal. First and second gates connect the ferroelectric memory cell to the bit lines in response to the word select circuit selecting that ferroelectric memory cell.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory comprising: first and second bit lines; and a plurality of ferroelectric memory cells connected between said first and second bit lines; a word select circuit that selects one of said ferroelectric memory cells, a read circuit that generates a potential on said first bit line indicative of a value stored in said selected one of said plurality of ferroelectric memory cells, each ferroelectric memory cell comprising; a ferroelectric capacitor characterized by first and second polarization states; a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal, said ferroelectric capacitor being connected between said control terminal and said first switch terminal; a first gate that connects said first switch terminal to said bit line in response to said word select circuit selecting that ferroelectric memory cell; and a second gate that connects said control terminal to said second bit line in response to said word select circuit selecting that ferroelectric memory cell.
2. The memory of claim 1 wherein said read circuit comprises a conductive load that is connected between a power terminal and said first bit line.
3. The memory of claim 1 wherein said read circuit comprises a conductive load connected between a power terminal and said first switch terminal.
4. The memory of claim 2 wherein said conductive load varies in time during a period of time in which said selected ferroelectric memory cell is connected to said first and second bit lines.
5. The memory of claim 1 wherein said read circuit further comprises a feedback element that resets said polarization state to said first polarization state if said polarization state switches from said first state to said second state in response to being connected to said first bit line.
6. The memory of claim 5 wherein said feedback circuit comprises a switch that connects said second bit line to a power terminal in response to a potential on said first bit line.
7. The memory of claim 5 wherein said feedback circuit comprises a switch that connects a power terminal to said control terminal.
8. The memory of claim 1 further comprising a charge-to-voltage converter connected to said second bit line.
9. The memory of claim 8 wherein said charge-to-voltage converter comprises a capacitor having a ferroelectric dielectric.
10. The memory of claim 1 further comprising a write circuit that receives a data signal and couples predetermined potentials determined by said data signal to said first and second bit lines.
11. The memory of claim 1 wherein said switch in one of said ferroelectric memory cells comprises a bi-polar transistor, a field effect transistor, a ferroelectric field effect transistor, a relay, or circuits constructed from a plurality of such elements.
12. A method for reading data from a memory comprising a plurality of ferroelectric memory cells that are reversibly connectable to first and second bit lines, each ferroelectric memory cell comprising: a ferroelectric capacitor characterized by first and second polarization states; a variable impedance element having an impedance between first and second switch terminals that is determined by a signal on a control terminal, said ferroelectric capacitor being connected between said control terminal and said first switch terminal; a first gate that connects said first switch terminal to said bit line in response to said word select circuit selecting that ferroelectric memory cell; and a second gate that connects said control terminal to said second bit line in response to said word select circuit selecting that ferroelectric memory cell, said method comprising the steps of: (a) connecting one of said ferroelectric memory cells between first and second bit lines while leaving the remaining ferroelectric memory cells disconnected from said first and second bit lines; (b) applying power to said connected ferroelectric memory cells after said ferroelectric memory cells has been connected to said first and second bit lines; (c) sensing a state for said ferroelectric memory cells by measuring a signal on one of said bit lines; (d) outputting a signal indicative of said state on an output line; (e) disconnecting said ferroelectric memory cell from said bit lines; and (f) removing power from said bit lines.
13. The method of claim 12 wherein steps (e) and (f) are performed in parallel with step (d).
14. The method of claim 12 wherein said ferroelectric capacitor is in a first state when said ferroelectric memory cell is connected to said bit lines and wherein said method further comprising the step of (d1) causing said ferroelectric capacitor in said connected ferroelectric memory cell to be reset to first state prior to removing power from said bit lines.
15. The method of claim 14 wherein steps (d1), (e), and (f) are performed in parallel with step (d).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 9, 2010
November 13, 2012
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