Methods for estimating a distance between an originator and a transponder, methods for calculating a fine time adjustment in a radio, computer-readable storage media containing instructions to configure a processor to perform such methods, originators used in a system for estimating a distance to a transponder, and transponders used in a system for estimating a distance to an originator. The methods utilize fine time adjustments to achieve sub-clock cycle time resolution. The methods may utilize offset master clocks. The methods may utilize a round-trip full-duplex configuration or a round-trip half-duplex configuration. The method produces accurate estimates of the distance between two radios.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for calculating a fine time adjustment in a radio, the method comprising: receiving at a processor an output from a correlator; calculating a plurality of peak error measurements of a correlator output in said radio during a time period; calculating a rate of change of said plurality of peak error measurements; estimating a peak error at a point after said time period by using said rate of change of said plurality of peak error measurements; and normalizing said estimated peak error.
2. The method of claim 1 , wherein said radio is an originator and, during said normalizing step, said estimated peak error is divided by a master clock frequency of a first channel of said originator.
3. The method of claim 1 , wherein said radio is a transponder and, during said normalizing step, said estimated peak error is divided by a master clock frequency of said transponder.
4. The method of claim 1 , wherein said radio is an originator and, during said normalizing step, said estimated peak error is divided by a master clock frequency of said originator.
5. The method of claim 1 , wherein said plurality of peak error measurements are scaled such that the possible range of values is between approximately −0.5 and 0.5.
6. The method of claim 1 , wherein said output received from a correlator is oversampled compared to a PN sequence input to said correlator.
7. The method of claim 6 , wherein said output received from a correlator is oversampled approximately four times said PN sequence input to said correlator.
8. A processor for calculating a fine time adjustment within a radio, the processor comprising: a calculating means for calculating a plurality of peak error measurements using output received from a correlator in said radio during a time period; a calculating means for calculating a rate of change of said plurality of peak error measurements; an estimating means for estimating a peak error at a point after said time period by using said rate of change of said plurality of peak error measurements; and a normalizing means for normalizing said estimated peak error.
9. The processor of claim 8 , wherein said radio is an originator and, during said normalizing step, said estimated peak error is divided by a master clock frequency of a first channel of said originator.
10. The processor of claim 8 , wherein said radio is a transponder and, during said normalizing step, said estimated peak error is divided by a master clock frequency of said transponder.
11. The processor of claim 8 , wherein said radio is an originator and, during said normalizing step, said estimated peak error is divided by a master clock frequency of said originator.
12. The processor of claim 8 , wherein said plurality of peak error measurements are scaled such that the possible range of values is between approximately −0.5 and 0.5.
13. The processor of claim 8 , wherein said output received from a correlator is oversampled compared to a PN sequence input to said correlator.
14. The processor of claim 13 , wherein said output received from a correlator is oversampled approximately four times said PN sequence input to said correlator.
15. The processor of claim 8 , wherein said processor is a field programmable gate array.
16. The processor of claim 8 , wherein said processor is an integrated circuit.
17. The processor of claim 8 , wherein said processor is a digital signal processor.
18. The processor of claim 8 , wherein said processor is a microcontroller.
19. The processor of claim 14 , wherein said processor is a field programmable gate array.
20. The processor of claim 14 , wherein said processor is an integrated circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 24, 2012
November 20, 2012
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