A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a substrate having an upper surface and a lower surface; a gate structure provided proximate to the upper surface of the substrate, the gate structure comprising a gate insulation layer, a first electrode over the gate insulation layer, an intermediate structure over the first electrode, and a second electrode over the intermediate structure, wherein the intermediate structure comprises a first Ti layer including titanium, a second Ti layer including titanium nitride formed over the first Ti layer, a first W layer including tungsten formed over the second Ti layer, and a second W layer including tungsten and silicon formed over the first W layer, wherein the first Ti layer is a titanium silicide (TiSi x ) layer.
2. The device of claim 1 , wherein: x in the TiSi x layer is approximately 2; and the second W layer is a tungsten silicide layer.
3. The device of claim 1 , wherein the first Ti layer, the second Ti layer, and the first W layer are derived from a thermal treatment of a titanium layer and a tungsten nitride layer.
4. The device of claim 3 , wherein the tungsten nitride layer has a nitrogen content of approximately 10% to 50% and is approximately 50 Å to 100 Å thick.
5. The device of claim 3 , wherein the titanium layer is formed to a thickness of approximately 50 Å or less.
6. The device of claim 5 , wherein the titanium layer is formed to a thickness of approximately 5 Å to 30 Å.
7. The device of claim 1 , further comprising a third Ti layer provided between the first W layer and the second W layer, the third Ti layer including titanium nitride.
8. The device of claim 7 , wherein the titanium nitride of the third Ti layer has a nitrogen content of approximately 10% to 50% and is formed to a thickness of approximately 40 Å to 200 Å.
9. The device of claim 1 , further comprising: a third W layer provided over the second W layer and including tungsten silicon nitride.
10. The device of claim 9 , wherein the tungsten silicon nitride is derived from a thermal treatment of a tungsten silicide layer and a tungsten nitride layer.
11. The device of claim 10 , wherein the tungsten silicide layer includes an amorphous tungsten silicide (WSi x ) layer, where x ranges between approximately 2 and 5.
12. The device of claim 1 , wherein the first electrode is a polysilicon-based electrode doped with a P-type impurity.
13. The device of claim 12 , wherein the P-type impurity includes boron (B).
14. The device of claim 1 , wherein the gate structure is formed in a dual gate structure, comprising: a first gate structure comprising an N-type impurity doped polysilicon-based electrode and a tungsten electrode, wherein the N-type impurity doped polysilicon-based electrode is formed underneath the intermediate structure, and the tungsten electrode is formed over the intermediate structure; and a second gate structure comprising a P-type impurity doped polysilicon-based electrode and a tungsten electrode, wherein the P-type impurity doped polysilicon-based electrode is formed underneath the intermediate structure and the tungsten electrode is formed over the intermediate structure.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 23, 2010
November 27, 2012
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