A method and system to lower the minimum operating voltage of a register file without increasing the area of each bit cell of the register file. In one embodiment of the invention, the register file is coupled to logic that reduces the contention between the NMOS devices and the PMOS devices in each bit cell of the register file during write and/or read operations of the register file. By doing so, the register file is able to operate at a lower minimum operating voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: a bit cell having a first storage node to store a value asserted on a write bit line, and a second storage node to store a value asserted via a second write bit line that is complementary to the first write bit line value; and a circuit, including: a pull up switch circuit to selectively apply an operating voltage to one of a first voltage node coupled to the first storage node and a second voltage node coupled to the second storage node, under control of the complementary write bit line values; and a voltage equalizer connected between the first and second voltage nodes, wherein, during a write to the bit cell, one of the first and second storage nodes into which a write bit line value of logic 1 is to be written is pulled up strongly to the operating voltage through the switch circuit, and the other of the first and second storage nodes into which a write bit line value of logic 0 is to be written is pulled up weakly through both the switch circuit and the voltage equalizer connected in series.
2. The circuit of claim 1 , wherein the pull up switch circuit includes: a first transistor to selectively apply the operating voltage to the first voltage node under control of the first write bit line value; and a second transistor to selectively apply the operating voltage to the second voltage node under control of the complementary second write bit line value, wherein to write the write bit line values of logic 1 and logic 0 to the first and second storage nodes, respectively, the first storage node is pulled up strongly to the operating voltage through the first transistor, and the second storage node is pulled up weakly to the operating voltage through the first transistor and the equalizer connected in series, and wherein to write the write bit line values of logic 0 and logic 1 to the first and second storage nodes, respectively, the first storage node is pulled up weakly to the operating voltage through the second transistor and the voltage equalizer connected in series, and the second storage node is pulled up strongly to the operating voltage through the second transistor.
3. The circuit of claim 1 , wherein: the pull up switch circuit includes a transistor source-drain current path through which the operating voltage is selectively applied to the one of the first and second voltage nodes; and the voltage equalizer includes at least one transistor source-drain current path connected between the first and second voltage nodes, such that the one of the first and second storage nodes to which the logic one is to be written is pulled up strongly through the pull up circuit transistor source-drain current path, and the other of the first and second storage nodes to which the logic 0 is to be written is pulled up weakly through the pull up circuit transistor source-drain current path and the voltage equalizer at least one transistor source-drain current path connected in series.
4. The circuit of claim 1 , wherein the voltage equalizer includes first and second transistors having their source-drain current paths connected in series between the first and second voltage nodes and each of their gates connected a voltage supply rail to keep the first and second transistors always turned on.
5. The circuit of claim 4 , wherein the pull up switch circuit includes: a first switch transistor having a source-drain current path connected between the operating voltage and the first voltage node, and a gate controlled by the first write bit line; and a second switch transistor having a source-drain current path connected between the operating voltage and the second voltage node, and a gate controlled by the second write bit line.
6. The circuit of claim 1 , wherein the circuit further comprises a pull down weakening circuit, coupled to the first and second storage nodes, to weaken a pull down strength applied to the first and second storage nodes.
7. The circuit of claim 1 , wherein the bit cell further comprises first and second cross-coupled inverters, the first inverter including a bit cell first pull up transistor coupled between the first storage node and the first voltage node, the second inverter including a bit cell second pull up transistor coupled between the second storage node and the second voltage node, wherein during the write to the bit cell the first and second storage nodes are pulled up to the operating voltage through the respective bit cell first and second pull up transistors and at least one of the switch circuit and the voltage equalizer, under control of the write line bit values.
8. The circuit of claim 7 , wherein the first inverter further includes a bit cell first pull down transistor coupled between the first storage node and a pull down voltage node, and the bit cell second inverter further includes a bit cell second pull down transistor coupled between the second storage node and the pull down voltage node, the circuit further comprising a pull down weakening transistor having its source-drain current path connected between the pull down voltage node and a ground potential.
9. The circuit of claim 1 , wherein the circuit further includes a logic retention circuit to provide a retention voltage to the first and second voltage nodes under control of a write enable signal so that the retention voltage is applied when the write to the bit cell does not occur.
10. The circuit of claim 9 , wherein the logic retention circuit includes: a logic retention first switch transistor having a source-drain current path connected between the operating voltage and the first voltage node, and a gate controlled by the write enable signal; and a logic retention second switch transistor having a source-drain current path connected between the operating voltage and the second voltage node, and a gate controlled by the write enable signal.
11. A system, comprising: a memory to store instructions; a processor to execute the instructions stored in memory; and a display device connected with the processor and the memory, wherein the processor includes memory having: a bit cell having a first storage node to store a value asserted on a write bit line, and a second storage node to store a value asserted via a second write bit line that is complementary to the first write bit line value; and a circuit, including: a pull up switch circuit to selectively apply the operating voltage to one of a first voltage node coupled to the first storage node and a second voltage node coupled to the second storage node, under control of the complementary write bit line values; and a voltage equalizer connected between the first and second voltage nodes, wherein, during a write to the bit cell, one of the first and second storage nodes into which a write bit line value of logic 1 is to be written is pulled up strongly to the operating voltage through the switch circuit, and the other of the first and second storage nodes into which a write bit line value of logic 0 is to be written is pulled up weakly through both the switch circuit and the voltage equalizer connected in series.
12. The system of claim 11 , wherein the pull up switch circuit includes: a first transistor to selectively apply the operating voltage to the first voltage node under control of the first write bit line value; and a second transistor to selectively apply the operating voltage to the second voltage node under control of the complementary second write bit line value, wherein to write the write bit line values of logic 1 and logic 0 to the first and second storage nodes, respectively, the first storage node is pulled up strongly to the operating voltage through the first transistor, and the second storage node is pulled up weakly to the operating voltage through the first transistor and the equalizer connected in series, and wherein to write the write bit line values of logic 0 and logic 1 to the first and second storage nodes, respectively, the first storage node is pulled up weakly to the operating voltage through the second transistor and the voltage equalizer connected in series, and the second storage node is pulled up strongly to the operating voltage through the second transistor.
13. The system of claim 11 , wherein: the pull up switch circuit includes a transistor source-drain current path through which the operating voltage is applied to the one of the first and second voltage nodes; and the voltage equalizer includes at least one transistor source-drain current path connected between the first and second voltage nodes, such that the one of the first and second storage nodes to which the logic one is to be written is pulled up strongly through the pull up circuit transistor source-drain current path, and the other of the first and second storage nodes to which the logic 0 is to be written is pulled up weakly through the pull up circuit transistor source-drain current path and the voltage equalizer at least one transistor source-drain current path connected in series.
14. The system of claim 11 , wherein the voltage equalizer includes first and second transistors having their source-drain current paths connected in series between the first and second voltage nodes and each of their gates connected to a voltage supply rail to keep the first and second transistors always turned on.
15. The system of claim 14 , wherein the pull up switch circuit includes: a first switch transistor having a source-drain current path connected between the operating voltage and the first voltage node, and a gate controlled by the first write bit line; and a second switch transistor having a source-drain current path connected between the operating voltage and the second voltage node, and a gate controlled by the second write bit line.
16. The system of claim 11 , wherein the circuit further comprises a pull down weakening circuit, coupled to the first and second storage nodes, to weaken a pull down strength applied to the first and second storage nodes.
17. The system of claim 11 , wherein the bit cell further comprises first and second cross-coupled inverters, the first inverter including a bit cell first pull up transistor coupled between the first storage node and the first voltage node, the second inverter including a bit cell second pull up transistor coupled between the second storage node and the second voltage node, wherein during the write to the bit cell the first and second storage nodes are pulled up to the operating voltage through the respective bit cell first and second pull up transistors and at least one of the switch circuit and the voltage equalizer, under control of the write line bit values.
18. The system of claim 17 , wherein the first inverter further includes a bit cell first pull down transistor coupled between the first storage node and a pull down voltage node, and the bit cell second inverter further includes a bit cell second pull down transistor coupled between the second storage node and the pull down voltage node, the circuit further comprising a pull down weakening transistor having its source-drain current path connected between the pull down voltage node and a ground potential.
19. The system of claim 11 , wherein the circuit further includes a logic retention circuit to provide a retention voltage to the first and second voltage nodes under control of a write enable signal so that the retention voltage is applied when the write to the bit cell does not occur.
20. The system of claim 19 , wherein the logic retention circuit includes: a logic retention first switch transistor having a source-drain current path connected between the operating voltage and the first voltage node, and a gate controlled by the write enable signal; and a logic retention second switch transistor having a source-drain current path connected between the operating voltage and the second voltage node, and a gate controlled by the write enable signal.
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March 26, 2010
November 27, 2012
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