A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device comprising: a memory array; and a memory control circuit coupled to the memory array and configured to control operation of the memory device, the control circuit configured to control programming of a group of memory cells of the memory array by controlling a bias of a selected word line WL n at a program voltage, controlling a bias of word lines WL n+2 and WL n−2 at V pass — L , controlling a bias of word lines WL n−3 and WL n−4 with decreasing voltages from V pass — L , and controlling a bias of remaining unselected word lines of the group of memory cells at V pass wherein V pass — L is less than V pass .
2. The device of claim 1 wherein WL n−3 >WL n−4 .
3. The device of claim 1 wherein V pass is greater than or equal to a read voltage.
4. The device of claim 3 wherein the read voltage is in a range of 0-2.5V.
5. The device of claim 1 wherein the memory array comprises a plurality of MLC memory cells.
6. The device of claim 1 wherein WL n−3 =3.6V.
7. The device of claim 1 wherein WL n−4 =0V.
8. The device of claim 1 wherein the memory array comprises bit lines coupled to columns of the group of memory cells and the memory control circuit is further configured to control bias of bit lines inhibited from programming at an inhibit voltage.
9. The device of claim 8 wherein the inhibit voltage is V CC .
10. A memory device comprising: a memory array; and a memory control circuit coupled to the memory array and configured to control operation of the memory device, the control circuit configured to control programming of a group of memory cells of the memory array by controlling a bias of a selected word line WL n at a program voltage, controlling a bias of word lines WL n+2 and WL n−2 at V pass — L , controlling a bias of word line WL n−3 a voltage that is less than V pass — L , and controlling a bias of remaining unselected word lines of the group of memory cells at V pass wherein V pass — L is less than V pass .
11. The device of claim 10 wherein WL n−3 =0V.
12. The device of claim 10 wherein V pass is in a range of 8V-10V.
13. The device of claim 10 wherein the memory array comprises one of a NAND architecture, a NOR architecture, or an AND architecture.
14. The device of claim 10 wherein the memory array comprises non-volatile memory cells.
15. A system comprising: a controller configured to generate memory signals; and a memory device coupled to the controller configured to operate in response to the memory signals, the device comprising: a memory array; and a memory control circuit coupled to the memory array and configured to control operation of the memory device, the control circuit configured to control programming of a group of memory cells of the memory array, the memory control circuit configured to control a bias of a selected word line WL n ay a programming voltage, control a bias of word lines WL n+2 and WL n−2 at V pass — L , and control a bias of word line WL n−3 at a voltage that is less than V pass — L , and control a bias of remaining unselected word lines of the group of memory cells at V pass wherein V pass — L is less than V pass .
16. The system of claim 15 wherein the memory control circuit is further configured to control a bias of word line WL n−4 at a voltage that is less than the voltage on WL n−3 .
17. The system of claim 15 wherein V pass — L is greater than or equal to 2.5V.
18. The system of claim 15 wherein V pass is greater than V pass — L .
19. The system of claim 15 wherein the programming voltage comprises a series of pulses.
20. The system of claim 19 wherein the series of pulses are in a range of 15V to 21V.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 23, 2012
December 4, 2012
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