A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: (a) a semiconductor substrate of a substantially rectangular shape; (b) semiconductor elements formed over a main surface of said semiconductor substrate; (c) a first wiring layer formed over said semiconductor elements; (d) a first insulating film formed over said main surface of said semiconductor substrate to cover said first wiring layer; (e) a plurality of first pad electrodes and a plurality of second pad electrodes formed over said first insulating film; (f) a second wiring layer formed over said first insulating film, said second wiring layer being formed at a same level as said first and second pad electrodes; (g) a second insulating film to cover said first and second pad electrodes and said second wiring layer, said second insulating film having openings at upper sides of said first and second pad electrodes, respectively; and (h) a plurality of first bump electrodes and a plurality of second bump electrodes of substantially rectangular shape formed over said second insulating film, said first and second bump electrodes being electrically connected to corresponding ones of said first and second pad electrodes via said openings of said second insulating film, respectively, wherein said first pad electrodes and said first bump electrodes are for outputting signals and arranged in a zigzag pattern in plan view in a vicinity of a first long side of said semiconductor substrate, said first pad electrodes and said first bump electrodes being respectively arranged at predetermined intervals in a first direction which is along said first long side of said semiconductor substrate, wherein said second pad electrodes and said second bump electrodes are for inputting signals and arranged linearly in a vicinity of a second long side of said semiconductor substrate, said second pad electrodes and said second bump electrodes being respectively arranged at predetermined intervals in said first direction, wherein each of said first bump electrodes and each of said second bump electrodes are configured such that long sides thereof extend in a second direction which is along a first short side of said semiconductor substrate, and wherein said second wiring layer is disposed directly under at least said first bump electrodes or said second bump electrodes and extends along said first direction.
2. A semiconductor device according to claim 1 , wherein a third wiring layer is formed over said first insulating film, said third wiring layer being formed at a same level as said second wiring layer, wherein said second wiring layer is disposed directly under said first bump electrodes, and wherein said third wiring layer is disposed directly under said second bump electrodes.
3. A semiconductor device according to claim 1 , wherein, for each of said first and second bump electrodes, a width thereof in said first direction is smaller than a width of the corresponding pad electrode in said first direction, and wherein, for each of said first and second bump electrodes, a width thereof in said second direction is larger than a width of the corresponding pad electrode in said second direction.
4. A semiconductor device according to claim 1 , wherein said second insulating film is a silicon nitride film.
5. A semiconductor device according to claim 1 , wherein said first insulating film is a silicon oxide film.
6. A semiconductor device according to claim 1 , wherein each of said first and second bump electrodes is formed of a gold film.
7. A semiconductor device according to claim 1 , wherein each of said second wiring layer and said first and second pad electrodes includes an aluminum film, and wherein each of said second wiring layer and said first and second pad electrodes further includes, on each side of said aluminum film thereof, one of a titanium film and a titanium nitride film.
8. A semiconductor device according to claim 1 , wherein said second wiring layer includes a power wire.
9. A semiconductor device according to claim 1 , wherein said second wiring layer is formed of a conducting layer, said conducting layer not being formed between adjacent first pad electrodes or adjacent second pad electrodes.
10. A semiconductor device according to claim 1 , wherein said second wiring layer is a top layer interconnection wiring.
11. A semiconductor device according to claim 1 , wherein said semiconductor elements include a portion of circuits which drive a liquid crystal display.
12. A semiconductor device according to claim 11 , wherein said first bump electrodes are for gate output signals or source output signals.
13. A semiconductor device according to claim 11 , including additional pad electrodes and corresponding additional bump electrodes for outputting signals arranged in zigzag pattern in a vicinity of said first short side and a second short side of said semiconductor substrate and respectively arranged at predetermined intervals in said second direction.
14. A semiconductor device according to claim 13 , wherein said additional bump electrodes are for gate output signals.
15. A semiconductor device according to claim 11 , wherein said first bump electrodes include a plurality of third bump electrodes, a plurality of fourth bump electrodes, and a plurality of fifth bump electrodes, wherein said third bump electrodes are disposed in a vicinity of said first short side, wherein said fourth bump electrodes are disposed in a vicinity of a second short side of said semiconductor substrate, wherein said third and fourth bump electrodes are for gate output signals, wherein said fifth bump electrodes are disposed between said third and fourth bump electrodes in said first direction, and wherein said fifth bump electrodes are for source output signals.
16. A semiconductor device according to claim 1 , wherein said openings of said second insulating film are disposed near one short edge of said first and second bump electrodes.
17. A semiconductor device according to claim 1 , wherein said second bump electrodes are adapted to be electrically connected with a flexible printed circuit.
18. A semiconductor device comprising: (a) a semiconductor substrate of a substantially rectangular shape; (b) semiconductor elements formed over a main surface of said semiconductor substrate; (c) a first wiring layer formed over said semiconductor elements; (d) a first insulating film formed over said main surface of said semiconductor substrate to cover said first wiring layer; (e) a plurality of first pad electrodes, a plurality of second pad electrodes, and a plurality of third pad electrodes formed over said first insulating film; (f) a second wiring layer formed over said first insulating film, said second wiring layer being formed at a same level as said first, second, and third pad electrodes; (g) a second insulating film to cover said first, second, and third pad electrodes and said second wiring layer, said second insulating film having openings at upper sides of said first, second, and third pad electrodes, respectively; and (h) a plurality of first bump electrodes, a plurality of second bump electrodes, a plurality of third bump electrodes of substantially rectangular shape formed over said second insulating film, said first, second, and third bump electrodes being electrically connected to corresponding ones of said first, second, and third pad electrodes via said openings of said second insulating film, respectively, wherein said first, second, and third bump electrodes are arranged linearly at predetermined intervals in a first direction which is along a first long side of said semiconductor substrate, wherein said first and second bump electrodes are disposed in a vicinity of said first long side of said semiconductor substrate and arranged in a zigzag pattern in plan view, wherein said first and second bump electrodes are for outputting signals, wherein said third bump electrodes are disposed in a vicinity of a second long side of said semiconductor substrate, wherein said third bump electrodes are for inputting signals, wherein each of said first bump electrodes, each of said second bump electrodes, and each of third bump electrodes are configured such that long sides thereof extend in a second direction which is along a first short side of said semiconductor substrate, and wherein said second wiring layer is disposed directly under at least said first bump electrodes, said second bump electrodes, or said third bump electrodes and extends along said first direction.
19. A semiconductor device according to claim 18 , wherein said second wiring layer is disposed directly under said first bump electrodes or second bump electrodes.
20. A semiconductor device according to claim 18 , wherein a third wiring layer is formed over said first insulating film, said third wiring layer being formed at a same level as said second wiring layer, wherein said second wiring layer is disposed directly under said first bump electrodes, and wherein said third wiring layer is disposed directly under said second bump electrodes.
21. A semiconductor device according to claim 20 , wherein a fourth wiring layer is formed over said first insulating film, said third wiring layer being formed at a same level as said second and third wiring layers, wherein said fourth wiring layer is disposed directly under said third bump electrodes.
22. A semiconductor device according to claim 18 , wherein, for each of said first, second, and third bump electrodes, a width thereof in said first direction is smaller than a width of the corresponding pad electrode in said first direction, and wherein, for each of said first, second, and third bump electrodes, a width thereof in said second direction is larger than a width of the corresponding pad electrode in said second direction.
23. A semiconductor device according to claim 18 , wherein said openings are disposed near one short edge of said first, second, and third bump electrodes.
24. A semiconductor device according to claim 18 , wherein said second insulating film is a silicon nitride film.
25. A semiconductor device according to claim 18 , wherein said first insulating film is a silicon oxide film.
26. A semiconductor device according to claim 18 , wherein each of said first and second bump electrodes is formed of a gold film.
27. A semiconductor device according to claim 18 , wherein each of said second wiring layer and said first, second, and third pad electrodes includes an aluminum film, and wherein each of said second wiring layer and said first, second, and third pad electrodes further includes, on each side of said aluminum film thereof, one of a titanium film and a titanium nitride film.
28. A semiconductor device according to claim 18 , wherein said second wiring layer includes a power wire.
29. A semiconductor device according to claim 18 , wherein said second wiring layer is formed of a conducting layer, said conducting layer not being formed between adjacent first pad electrodes, adjacent second pad electrodes, or adjacent third pad electrodes.
30. A semiconductor device according to claim 18 , wherein said second wiring layer is a top layer interconnection wiring.
31. A semiconductor device according to claim 18 , wherein said semiconductor elements include a portion of circuits which drive a liquid crystal display.
32. A semiconductor device according to claim 31 , wherein said first, second, and third bump electrodes are for gate output signals or source output signals.
33. A semiconductor device according to claim 31 , including additional pad electrodes and corresponding additional bump electrodes for outputting signals arranged in zigzag pattern in a vicinity of said first short side and a second short side of said semiconductor substrate and respectively arranged at predetermined intervals in said second direction.
34. A semiconductor device according to claim 33 , wherein said additional bump electrodes are for gate output signals.
35. A semiconductor device according to claim 31 , wherein said first bump electrodes include a plurality of fourth bump electrodes, a plurality of fifth bump electrodes, and a plurality of sixth bump electrodes, wherein said second bump electrodes include a plurality of seventh bump electrodes, a plurality of eighth bump electrodes, and a plurality of ninth bump electrodes, wherein said fourth and seventh bump electrodes are disposed in a vicinity of said first short side of said semiconductor substrate, wherein said fifth and eighth bump electrodes are disposed in a vicinity of a second short side of said semiconductor substrate, wherein said sixth bump electrodes are disposed between said fourth and fifth bump electrodes in said first direction, wherein said ninth bump electrodes are disposed between said seventh and eighth bump electrodes in said first direction, wherein said fourth, fifth, seventh, and eighth bump electrodes are for gate output signals, and wherein said sixth and ninth bump electrodes are for source output signals.
36. A semiconductor device according to claim 31 , wherein said third bump electrodes are adapted to be electrically connected with a flexible printed circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 14, 2012
December 25, 2012
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