A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: a memory array including a first bitline to communicate first information during a read operation, the first information including first storage state information from one of a first plurality of memory cells, a second bitline to communicate second information during the read operation, the second information including second storage state information from one of a second plurality of memory cells, a third bitline to communicate third information during the read operation, the third information including third storage state information from one of a third plurality of memory cells during the read operation, a fourth bitline to communicate fourth information during the read operation, the fourth information including fourth storage state information from one of a fourth plurality of memory cells, a fifth bitline to communicate fifth information during the read operation, the fifth information including fifth storage state information from one of a fifth plurality of memory cells; a first sense amplifier including a first input coupled to the first bitline to receive the first information, a second input coupled to the second bitline to receive the second information, a third input coupled to the third bitline to receive the third information, and an output to provide an indicator of the first storage state information based upon the first information, the second information and the third information; a second sense amplifier including a first input coupled to the second bitline to receive the second information, a second input coupled to the fourth bitline to receive the fourth information, a third input coupled to the first bitline to receive the first information, and an output to provide an indicator of the second storage state information based upon the second information, the fourth information and the first information; and a third sense amplifier including a first input coupled to the third bitline to receive the third information, a second input coupled to the first bitline to receive the first information, a third input coupled to the fifth bitline to receive the fifth information, and an output to provide an indicator of the third storage state information based upon the third information, the first information and the fifth information.
2. The device of claim 1 wherein the first sense amplifier comprises a spatial filter to determine the indicator of the first storage state information based upon a physical relationship between the first bitline and at least one other bitline.
3. The device of claim 2 wherein the spatial filter of the first sense amplifier is to determine the indicator of the first storage state information based upon a physical relationship between the first bitline and the second bitline.
4. The device of claim 3 wherein the second sense amplifier comprises a spatial filter to determine the indicator of the second storage state information based upon a physical relationship between the second bitline and the first bitline.
5. The device of claim 2 , wherein the spatial filter comprises a summing module including an output to provide a first intermediate information based upon the first information, the second information and the third information, the first intermediate information used to determine the indicator of the first storage state information.
6. The device of claim 1 , wherein the first bitline is between the second bitline and the third bitline, the second bitline is between the fourth bitline and the first bitline, and the third bitline is between the first bitline and the fifth bitline.
7. The device of claim 6 wherein the first sense amplifier comprises a spatial filter to determine the indicator of the first storage state information based upon a physical relationship between the first bitline and the second bitline and not based upon a physical relationship between the first and fourth bitline.
8. The device of claim 6 wherein the first sense amplifier comprises a spatial filter to determine the indicator of the first storage state information based upon a physical relationship between the first bitline and the second bitline and based upon a physical relationship between the first and fourth bitline.
9. The device of claim 1 wherein the first sense amplifier comprises a spatial filter to determine the indicator of the first storage state information based upon a physical relationship between a first plurality of bitlines that includes the first bitline, and the second sense amplifier comprises a spatial filter to determine the indicator of the second storage state information based upon a physical relationship between a second plurality of bitlines that includes the second bitline.
10. The device of claim 1 wherein the first sense amplifier comprises a spatial filter that determines the indicator of the first storage state information based upon a physical relationship amongst the first bitline, the second bitline, and the third bitline.
11. The device of claim 1 , wherein the first sense amplifier comprises a summing amplifier including a first input coupled to the first bitline, a second input coupled to the second bitline, and a third input coupled to the third bitline, and an output to provide a first intermediate information used to determine the indicator of the first storage state information.
12. A device comprising: a memory array including a first bitline coupled to communicate first information during a read operation, including first storage state information from one of a first plurality of memory cells, a second bitline coupled to communicate second information, including second storage state information during the read operation from one of a second plurality of memory cells, and a third bitline coupled to communicate third information during the read operation, including third storage state information from one of a third plurality of memory cells; and a first sense amplifier comprising a summing amplifier, a storage state detect module, a first input coupled to the first bitline, a second input coupled to the second bitline, and a third input coupled to the third bitline, the summing amplifier comprising an output to provide an intermediate information based upon the first information, the second information and the third information, and the storage state detect module coupled to the output of the summing amplifier to determine an indicator of the storage state of the one of the first plurality of memory cells during the read operation based upon the intermediate information.
13. The device of claim 12 , wherein the indicator of the storage state of the one of the first plurality of memory cells is a logic value.
14. The device of claim 13 , wherein the logic value is a binary logic value.
15. The device of claim 12 , wherein the memory array further comprises a fourth bitline coupled to communicate fourth information during the read operation, including fourth storage state information from one of a first plurality of memory cells, and the device further comprising: a second sense amplifier comprising a summing amplifier, a storage state detect module, a first input coupled to the second bitline, a second input coupled to the third bitline, and a third input coupled to the fourth bitline, the summing amplifier comprising an output to provide an intermediate information based upon the first information, the second information and the fourth information, and the storage state detect module coupled to the output of the summing amplifier to determine an indicator of the storage state of the one of the second plurality of memory cells during the read operation based upon the intermediate information.
16. A device comprising: a memory array including a first bitline coupled to communicate first information, including first storage state information from one of a first plurality of memory cells, a second bitline coupled to communicate second information, including second storage state information from one of a second plurality of memory cells, and a third bitline coupled to communicate third information, including third storage state information, from one of a third plurality of memory cells; and a first sense amplifier comprising a first spatial filter having a first input coupled to the first bitline, a second input coupled to the second bitline, a third input coupled to the third bitline, and an output to provide a first intermediate information during a read operation based upon the first information, the second information and the third information, and based upon a physical relationship between the first bitline, the second bitline and the third bitline.
17. A method comprising: receiving via a first bitline, at a first input of a first sense amplifier, first information during a read operation, the first information including first storage state information from one of a first plurality of memory cells; receiving via a second bitline, at a second input of the first sense amplifier, second information during the read operation, the second information including second storage state information from one of a second plurality of memory cells; receiving via a third bitline, at a third input of the first sense amplifier, third information during the read operation, the third information including third storage state information from one of a third plurality of memory cells; and determining at the first sense amplifier an indicator corresponding to the first storage state information, wherein the indicator is determined based upon the first information, the second information and the third information.
18. The method of claim 17 further comprising: receiving, at a first input of a second sense amplifier, the second information via the first bitline during the read operation; receiving, at a second input of the second sense amplifier, the first information via the second bitline during the read operation; receiving via a fourth bitline, at a third input of the second sense amplifier, fourth information during the read operation, the fourth information including fourth storage state information from one of a fourth plurality of memory cells; and determining at the second sense amplifier an indicator corresponding to the second storage state information, wherein the indicator is determined based upon the second information, the first information and the fourth information.
19. The method of claim 18 , wherein the first bitline is between the second bitline and the third bitline, and the second bitline is between the first bitline and the fourth bitline.
20. The method of claim 17 , wherein determining further comprises filtering the first information, the second information, and the third information based a physical relationship amongst the first bitline, the second bitline, and the third bitline.
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April 27, 2010
December 25, 2012
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