The invention concerns a nanostructured device (100) comprising a substrate (101), an intermediate layer (102), a zone (103) consisting of multiple three-dimensional structured sites (104) made of semiconductor material, having chemical species (106) fixed to the surface of said three-dimensional nanostructured sites (104). The inventive device is useful for making a biochip and an electronic memory. The invention also concerns a method for forming an electronic memory.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nanostructured device ( 100 ), comprising a substrate ( 101 ), an intermediate layer ( 102 ), a zone ( 103 ) comprising a multitude of three-dimensional nanostructured sites ( 104 ), produced directly on the intermediate layer, in the form of grains, said nanostructures being capable of receiving chemical species ( 106 ) after the production of said sites, wherein the surfaces of the three-dimensional nanostructured sites ( 104 ) are equipped with a tie layer ( 204 ), which tie layer ( 204 ) is porous; or wherein the three-dimensional nanostructured sites ( 104 ) are separated from one another, and wherein the grains are porous.
2. The device as claimed in claim 1 , wherein the chemical species are attached to the nanostructured sites ( 104 ) by covalent bonds.
3. A nanostructured device ( 100 ), comprising a substrate ( 101 ), an intermediate layer ( 102 ), a zone ( 103 ) comprising a multitude of three-dimensional nanostructured sites ( 104 ), produced directly on the intermediate layer, in the form of grains, said nanostructures being capable of receiving chemical species ( 106 ) after the production of said sites, wherein the three-dimensional nanostructured sites ( 104 ) are separated from one another, and wherein the grains are porous.
4. The device as claimed in claim 1 , wherein the surface of the tie layer ( 204 ) is equipped with chemical coupling functional groups.
5. The device as claimed in claim 1 , wherein the substrate ( 101 ) is a material comprising silicon, germanium, or quartz or a mixture thereof.
6. The device as claimed in claim 5 , wherein the intermediate layer ( 102 ) is a dielectric or insulating material.
7. The device as claimed in claim 6 , wherein the dielectric is selected from the group consisting of oxides, nitrides, oxynitrides, carbides, oxycarbides and silicates of Si, Al, Hf, Zr or Ti.
8. The device as claimed in claim 1 , wherein the three-dimensional nanostructured sites ( 104 ) are grains having a hemispherical or spherical shape.
9. The device as claimed in claim 8 , wherein the grains have a diameter between 2 and 150 nm.
10. The device as claimed in claim 9 , wherein the density of the grains on the intermediate layer ( 102 ) is in the range between 10 6 and 10 12 cm −2 .
11. The device as claimed in claim 1 , wherein the chemical species ( 106 ) are selected from the group consisting of nucleic acids, peptides, proteins, enzymes, antibodies, lipids, their biological partners, compounds having redox properties, metallocenes, metalloporphyrins and polyoxometallates.
12. A biochip comprising a multitude of devices as claimed in claim 1 .
13. The device as claimed in claim 1 , wherein the chemical species are covered with a dielectric layer.
14. The device as claimed in claim 13 , wherein a layer made of a conductive material is located on top of the dielectric layer.
15. An electronic memory comprising a multitude of devices as claimed in claim 14 which are interconnected.
16. The electronic memory as claimed in claim 15 , wherein the multitude of devices forms a control gate.
17. The electronic memory as claimed in claim 16 comprising a source and a drain.
18. The electronic memory as claimed in claim 17 having an encapsulation layer which is made of an electronically-conductive material or from an electrically-insulating material.
19. A process for manufacturing a device as claimed in claim 1 , the process comprising the following successive steps: a) providing a substrate ( 101 ); b) forming an intermediate layer ( 102 ) on the surface of the substrate ( 101 ); c) producing three-dimensional nanostructured sites ( 104 ) directly on the intermediate layer ( 102 ) in the form of grains; and d) tying chemical species ( 106 ) to the surface of the three-dimensional nanostructured sites ( 104 ).
20. The process as claimed in claim 19 , wherein a tie layer ( 204 ) is deposited on each nanostructured site ( 104 ).
21. The process as claimed in claim 20 , wherein the tie layer is activated by treatment with a compound that has functional groups capable of attaching chemical species via a covalent bond.
22. The process as claimed in claim 19 , wherein the chemical species ( 106 ) are selected from the group consisting of nucleic acids, peptides, proteins, enzymes, antibodies, lipids, their biological partners, compounds having redox properties, metallocenes, metalloporphyrins and polyoxometallates.
23. The process as claimed in claim 19 , which achieves the manufacturing of an electronic memory ( 400 ), wherein the substrate ( 101 ) is made of silicon ( 401 ) and comprises sacrificial gate zones ( 402 , 403 , 404 , 405 , 406 ), sources ( 407 ), drains ( 408 ), a silicided zone ( 409 ) and an encapsulation layer ( 410 ).
24. The process as claimed in claim 23 , the process comprising, before step b), the following step: b 1 ) removing the sacrificial gate by the gate zone ( 405 ) down to the surface of the substrate ( 401 ) in order to form a well ( 420 ) of defined size.
25. The process as claimed in claim 24 , wherein steps b) and c) are carried out by: b) forming an insulating layer ( 411 ) over the surface of the substrate ( 401 ) obtained in step b 1 ; and c) depositing nanostructured sites ( 412 ) over the insulating layer ( 411 ) at the bottom of the well ( 420 ).
26. The process as claimed in claim 25 , further comprising the following additional steps: e) applying a layer ( 414 ) of a control dielectric over the tied chemical species; and f) depositing a layer ( 415 ) made from a conductive material over the control dielectric layer ( 414 ).
27. The process as claimed in claim 23 , wherein the removal of the dummy gate is carried out by successive etching of layers 402 , 403 and 404 .
28. The process as claimed in claim 27 , wherein the formation of the insulating layer is carried out by oxidation of the substrate ( 401 ).
29. The process as claimed in claim 28 , wherein the deposition of nanostructured sites ( 412 ) is carried out by a CVD, LPCVD or inoculation/annealing method.
30. The process as claimed in claim 23 , wherein a tie layer ( 414 ) is deposited on each nanostructured site ( 412 ).
31. The process as claimed in claim 30 , wherein the tie layer ( 414 ) is activated by treatment with a compound that has functional groups capable of attaching chemical species via a covalent bond.
32. The process as claimed in claim 23 , wherein the chemical species are molecules that have at least two stable oxidation states.
33. The process as claimed in claim 32 , wherein the layer ( 414 ) of a control dielectric is formed by low-temperature deposition or by addition of an electrolyte gel.
34. A nanostructured device ( 100 ), comprising a substrate ( 101 ), an intermediate layer ( 102 ), a zone ( 103 ) comprising a multitude of three-dimensional nanostructured sites ( 104 ), produced directly on the intermediate layer, in the form of grains, said nanostructures being capable of receiving chemical species ( 106 ) after the production of said sites, wherein the surfaces of the three-dimensional nanostructured sites ( 104 ) are equipped with a tie layer ( 204 ), which tie layer ( 204 ) is porous.
35. A process for manufacturing a device as claimed in claim 34 , the process comprising the following successive steps: a) providing a substrate ( 101 ); b) forming an intermediate layer ( 102 ) on the surface of the substrate ( 101 ); c) producing three-dimensional nanostructured sites ( 104 ) directly on the intermediate layer ( 102 ) in the form of grains, and depositing a tie layer ( 204 ) on each nanostructured site ( 104 ).
36. A biochip comprising a multitude of devices as claimed in claim 34 .
37. The device as claimed in claim 3 , wherein the surfaces of the three-dimensional nanostructured sites ( 104 ) are equipped with a tie layer ( 204 ), wherein the tie layer ( 204 ) is porous.
38. A process for manufacturing a device as claimed in claim 3 , the process comprising the following successive steps: a) providing a substrate ( 101 ); b) forming an intermediate layer ( 102 ) on the surface of the substrate ( 101 ); and c) producing three-dimensional nanostructured sites ( 104 ) directly on the intermediate layer ( 102 ) in the form of grains.
39. A biochip comprising a multitude of devices as claimed in claim 3 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 24, 2006
January 1, 2013
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.