A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A capacitor comprising a plurality of dielectric layers, and a plurality of internal electrode layers provided between different ones of said dielectric layers, wherein: at least one of chamfered portions having a chamfer dimension of 0.6 mm or more and rounded portions having a radius of curvature of 0.6 mm or more are formed in at least one corner portion of an outer periphery of said capacitor; said capacitor has a warpage of less than 100 μm over an area from approximately 25 mm 2 to approximately 144 mm 2 ; and said dielectric layers in said chamfered portions or said rounded portions have chipping quantities of 0.5 mm or less in length, 0.5 mm or less in width and 0.5 mm or less in depth.
2. The capacitor as claimed in claim 1 , wherein the capacitor comprises four corner portions, and the chamfered portions are formed on the four corner portions, respectively.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 22, 2010
January 8, 2013
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