Semiconductor memory device

1. A semiconductor memory device comprising: a memory cell comprising a variable resistance element whose resistance varies by application of a voltage; a power supply circuit which outputs the voltage to be applied to the memory cell; an interconnection which is formed between the power supply circuit and the memory cell and supplies the voltage output from the power supply circuit to the memory cell; wherein the interconnection further comprises at least a first segment between a selection circuit and the power supply; a discharging circuit connected to the interconnection; a sense amplifier which detects information stored in the memory cell according to the voltage of the interconnection; and the selection circuit which switches a state between the interconnection, the sense amplifier, and the memory cell to one of a connection state and a disconnection state, wherein, in a first discharge operation, the discharging circuit discharges electric charge accumulated in the interconnection after a first operation of applying the voltage to the memory cell is ended and, in a second discharge operation, before a second operation of applying the voltage to the memory cell next is started, wherein the discharging circuit discharges electric charge accumulated in the interconnection when the selection circuit sets the connection state, and then the discharging circuit discharges the electric charge accumulated in the first segment when the selection circuit sets the disconnection state.

2. The semiconductor memory device according to claim 1 , wherein the discharging circuit discharges the electric charge accumulated in the interconnection immediately before the second operation is started.

3. The semiconductor memory device according to claim 1 , wherein the first operation and the second operation include any one operation of reading, setting, and resetting, and the setting operation changes the variable resistance element from a high-resistance state to a low-resistance state, and the resetting operation changes the variable resistance element from the low-resistance state to the high-resistance state.

4. The semiconductor memory device according to claim 1 , wherein the memory cell is arranged between a bit line and a word line, such that the memory cell is electrically connected to the bit line and the word line, and the selection circuit switches a state between the bit line or the word line and the interconnection to one of the connection state and the disconnection state.

5. The semiconductor memory device according to claim 1 , wherein the memory cell comprises a rectifying element connected to the variable resistance element.

6. The semiconductor memory device according to claim 5 , wherein the rectifying element includes a diode.

7. A semiconductor device comprising: a memory cell comprising a variable resistance element whose resistance varies by application of a voltage; a first interconnection connected to the memory cell; a power supply circuit which outputs the voltage to be applied to the memory cell; a second interconnection which is connected to the power supply circuit and to which the voltage is supplied from the power supply circuit; a selection circuit which is connected between the first interconnection and the second interconnection and switches a state between the first interconnection and the second interconnection to one of a connection state and a disconnection state; and a discharging circuit connected to the second interconnection, wherein, in a first discharge operation, the discharging circuit discharges electric charge accumulated in the second interconnection after a first operation of applying the voltage to the memory cell is ended and, in a second discharge operation, before a second operation of applying the voltage to the memory cell next is started, the discharging circuit discharges the electric charge accumulated in the first and the second interconnections when the selection circuit sets the connection state, and then the discharging circuit discharges the electric charge accumulated in the second interconnection when the selection circuit sets the disconnection state.

8. The semiconductor memory device according to claim 7 , wherein the discharging circuit discharges the electric charge accumulated in the second interconnection immediately before the second operation is started.

9. The semiconductor memory device according to claim 7 , further comprising: a sense amplifier which detects information stored in the memory cell according to a voltage of the second interconnection.

10. The semiconductor memory device according to claim 7 , wherein the first operation and the second operation include any one operation of reading, setting, and resetting, and the setting operation changes the variable resistance element from a high-resistance state to a low-resistance state, and the resetting operation changes the variable resistance element from the low-resistance state to the high-resistance state.

11. The semiconductor memory device according to claim 7 , wherein the first interconnection includes one of a bit line and a word line.

12. The semiconductor memory device according to claim 11 , wherein the memory cell is arranged between the bit line and the word line, such that the memory cell is electrically connected to the bit line and the word line, and the selection circuit switches a state between the bit line or the word line and the second interconnection to one of the connection state and the disconnection state.

13. The semiconductor memory device according to claim 7 , wherein the memory cell comprises a rectifying element connected to the variable resistance element.

14. The semiconductor memory device according to claim 13 , wherein the rectifying element includes a diode.