A clock frequency divider circuit in accordance with the present invention is capable of generating a clock signal that makes it possible to perform an expected proper communication operation in communication with a circuit operating by a clock having a different frequency, and includes a mask control circuit 20 and a mask circuit 10. The mask control circuit 20 includes a mask timing signal generation circuit 22 that generates a mask timing signal 29 used to preferentially mask a clock pulse at a timing other than communication timings among M clock pulses of the input clock signal based on a communication timing signal 26, and a mask restraint circuit 62 that carries out a process to restrain masking of a clock pulse at a communication timing. The mask circuit 10 generates an output clock signal by masking clock pulses of an input clock signal according to a mask signal 50 generated by the mask control circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A clock frequency divider circuit that generates an output clock signal obtained by dividing a frequency of an input clock signal into N/M (N is a positive integer and M is a positive integer greater than N) by masking (M-N) clock pulses among M clock pulses of the input clock signal based on a frequency division ratio defined as N/M, comprising: a mask control circuit comprising: a mask timing signal generation circuit that generates a mask timing signal used to preferentially masks a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among M clock pulses of the input clock signal based on a communication timing signal indicating the communication timing; and a mask restraint circuit that generates a mask signal obtained by processing the mask timing signal so that masking of the clock pulse is restrained at the communication timing; and a mask circuit that generates the output clock signal by masking a clock pulse of the input clock signal according to the mask signal generated by the mask control circuit.
2. The clock frequency divider circuit according to claim 1 , wherein the mask control circuit comprises a counter that generates a count value indicating a relative phase of the communication timing with respect to the input clock signal by counting a clock pulse of the input clock signal and resetting a count value when the count value reaches a denominator M of the frequency division ratio, and generates the mask signal based on the count value.
3. The clock frequency divider circuit according to claim 2 , further comprising an error detection circuit that determines whether or not the count value is a normal value for the communication timing, and when the count value is determined to be not a normal value, controls the counter so as to reset the count value.
4. A clock frequency divider circuit that generates an output clock signal obtained by dividing a frequency of an input clock signal into N/M (N is a positive integer and M is a positive integer greater than N) by masking (M-N) clock pulses among M clock pulses of the input clock signal based on a frequency division ratio defined as N/M, comprising: a counter that generates a count value indicating a relative phase of a communication timing with respect to the input clock signal by counting a clock pulse of the input clock signal and resetting a count value when the count value reaches a denominator M of the frequency division ratio; a mask control circuit comprising: a mask timing signal generation circuit that generates a mask timing signal used to preferentially masks a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among M clock pulses of the input clock signal based on the count value and a communication timing signal indicating the communication timing; and an error detection circuit that determines whether or not the count value is a normal value for the communication timing, and when the count value is determined to be not a normal value, controls the counter so as to reset the count value; and a mask circuit that generates the output clock signal by masking a clock pulse of the input clock signal according to the mask timing signal generated by the mask control circuit.
5. The clock frequency divider circuit according to claim 2 , wherein the mask timing signal generation circuit comprises a table circuit that holds in advance table data indicating necessity/non-necessity of masking for each combination of at least the counter value, and a frequency division ratio denominator M and a frequency division ratio numerator N of the frequency division ratio, and outputs table data output from the table circuit according to the input combination as the mask timing signal.
6. The clock frequency divider circuit according to claim 1 , further comprising a communication timing detection circuit that detects a rising edge timing of a clock signal input as a reference of a communication timing, and thereby generates the communication timing signal.
7. A clock frequency division method for generating an output clock signal obtained by dividing a frequency of an input clock signal into N/M (N is a positive integer and M is a positive integer greater than N) by masking (M-N) clock pulses among M clock pulses of the input clock signal based on a frequency division ratio defined as N/M, comprising: generating a mask timing signal used to preferentially masks a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among M clock pulses of the input clock signal based on a communication timing signal indicating the communication timing; generating a mask signal obtained by processing the mask timing signal so that masking of the clock pulse is restrained at the communication timing; and generating the output clock signal by masking a clock pulse of the input clock signal according to the mask signal.
8. The clock frequency divider method according to claim 7 , wherein a count value indicating a relative phase of the communication timing with respect to the input clock signal is generated by counting a clock pulse of the input clock signal and resetting a count value when the count value reaches a denominator M of the frequency division ratio, and the mask signal is generated based on the count value.
9. The clock frequency divider method according to claim 8 , wherein whether or not the count value is a normal value for the communication timing is determined, and when the count value is determined to be not a normal value, the count value is reset.
10. A clock frequency division method for generating an output clock signal obtained by dividing a frequency of an input clock signal into N/M (N is a positive integer and M is a positive integer greater than N) by masking (M-N) clock pulses among M clock pulses of the input clock signal based on a frequency division ratio defined as N/M, comprising: generating a count value indicating a relative phase of a communication timing with respect to the input clock signal by counting a clock pulse of the input clock signal and resetting a count value when the count value reaches a denominator M of the frequency division ratio; generating a mask timing signal used to preferentially masks a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among M clock pulses of the input clock signal based on the count value and a communication timing signal indicating the communication timing; determining whether or not the count value is a normal value for the communication timing, and when the count value is determined to be not a normal value, resetting the count value; and generating the output clock signal by masking a clock pulse of the input clock signal according to the mask timing signal.
11. The clock frequency divider method according to claim 8 , wherein table data indicating necessity/non-necessity of masking for each combination of at least the counter value, and a frequency division ratio denominator M and a frequency division ratio numerator N of the frequency division ratio is stored in advance, and the table data is output as the mask timing signal according to the input combination.
12. The clock frequency divider method according to claim 7 , wherein the communication timing signal is generated by detecting a rising edge timing of a clock signal input as a reference of a communication timing.
13. The clock frequency divider circuit according claim 4 , wherein the mask timing signal generation circuit comprises a table circuit that holds in advance table data indicating necessity/non-necessity of masking for each combination of at least the counter value, and a frequency division ratio denominator M and a frequency division ratio numerator N of the frequency division ratio, and outputs table data output from the table circuit according to the input combination as the mask timing signal.
14. The clock frequency divider circuit according to claim 4 , further comprising a communication timing detection circuit that detects a rising edge timing of a clock signal input as a reference of a communication timing, and thereby generates the communication timing signal.
15. The clock frequency divider method according to claim 10 , wherein table data indicating necessity/non-necessity of masking for each combination of at least the counter value, and a frequency division ratio denominator M and a frequency division ratio numerator N of the frequency division ratio is stored in advance, and the table data is output as the mask timing signal according to the input combination.
16. The clock frequency divider method according to claim 10 , wherein the communication timing signal is generated by detecting a rising edge timing of a clock signal input as a reference of a communication timing.
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December 2, 2009
February 5, 2013
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