Field effect transistor

1. A field effect transistor comprising: a semiconductor layer; source and drain electrodes in electrical contact with the semiconductor layer but spaced from one another so as to leave a channel region of the semiconductor layer therebetween; a gate dielectric layer superposed on the channel region of the semiconductor layer; and a gate electrode disposed on the opposed side of the gate dielectric layer from the channel region, such that variation of the voltage applied to the gate electrode can vary the conductivity of the channel region of the semiconductor layer, thus switching the transistor, the gate dielectric layer extending over at least portions of the source and drain electrodes adjacent the channel region, an auxiliary dielectric layer being provided between the overlapping portions of the gate dielectric layer and the source and drain electrodes, the auxiliary dielectric layer not being present in at least part of the channel region.

2. A field effect transistor according to claim 1 wherein the auxiliary dielectric layer has a thickness at least twice as great as that of the gate dielectric layer.

3. A field effect transistor according to claim 1 wherein the auxiliary dielectric layer is formed from a low k dielectric having a k value not greater than about 3.

4. A field effect transistor according to claim 1 wherein the auxiliary dielectric layer is formed from silicon dioxide, a polyimide or a screen printable dielectric.

5. A field effect transistor according to claim 1 wherein the gate electrode is formed by printing.

6. A field effect transistor array comprising at least two field effect transistors according to claim 1 disposed adjacent one another, wherein the gate dielectric is continuous from one transistor to the other.

7. An electro-optic display comprising a layer of an electro-optic medium, a front electrode disposed on one side of the layer of electro-optic medium, and a plurality of pixel electrodes disposed on the opposed side of the layer of electro-optic medium, the pixel electrodes being disposed in a plurality of rows and plurality of columns, each pixel electrode having a transistor associated therewith, the sources of all the transistors in each column being connected to a single column electrode, while the gates of all the transistors in each row are connected to a single row electrode, and wherein at least one transistor is a field effect transistor according to claim 1 .