The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse. In one embodiment, the controller may be adapted to adjust timing of a read clock pulse differently from a write clock pulse.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system comprising: a memory block; and a controller in communication with the memory block, the controller adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block.
2. The system of claim 1 , where the delay corresponds to time taken for the memory block to become activated.
3. The system of claim 1 , where the delay corresponds to a predecoder delay.
4. The system of claim 1 , where the delay corresponds to a global decoder delay.
5. The system of claim 1 , where the controller is adapted to extend the clock pulse using a word line interfacing with the controller.
6. The system of claim 1 , where the portion comprises a high portion of the clock pulse.
7. The system of claim 1 , where the memory block comprises a local memory block, and where the controller comprises a global controller for multiple memory blocks that include the local memory block.
8. The system of claim 1 , where the clock pulse comprises a write clock pulse.
9. The system of claim 1 , where the clock pulse comprises a read clock pulse.
10. The system of claim 1 , where the controller is adapted to adjust timing of a read clock pulse differently from a write clock pulse.
11. A method comprising: in a controller in communication with a memory block: adjusting timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block.
12. The method of claim 11 , where the delay corresponds to time taken for the memory block to become activated.
13. The method of claim 11 , where the delay corresponds to a predecoder delay.
14. The method of claim 11 , where the delay corresponds to a global decoder delay.
15. The method of claim 11 , where adjusting timing of a memory access operation comprises extending the clock pulse using a word line interfacing with the controller.
16. The method of claim 11 , where the portion comprises a high portion of the clock pulse.
17. The method of claim 11 , where the memory block comprises a local memory block, and where the controller comprises a global controller for multiple memory blocks that include the local memory block.
18. The method of claim 11 , where the clock pulse comprises a write clock pulse.
19. The method of claim 11 , where the clock pulse comprises a read clock pulse.
20. The method of claim 11 , where adjusting timing of a memory access operation comprises adjusting timing of a read clock pulse differently from adjusting timing of a write clock pulse.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 30, 2012
February 19, 2013
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