A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.
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1. A method for efficiently performing a multithreaded analysis of a timing graph of a circuit comprising: a. using a computer, identifying a plurality of timing analysis tasks comprising performing a common path pessimism removal and computer critical paths for timing reports and identifying associated sub-graphs of said timing graph of said circuit upon which each timing analysis task is to be performed; b. creating a plurality of child computational threads and assigning thereto at least one of said identified timing analysis tasks; c. creating in each of said plurality of child threads a thread-specific graph replica (TSGR) of said associated sub-graph of said timing graph of said circuit on which said at least one timing analysis task assigned thereto is to be performed; d. performing in each child thread said at least one timing analysis task assigned thereto, wherein all timing data generated and stored in said performance is stored in said TSGR of said associated sub-graph of said timing graph; and e. transferring results from each of said timing analysis task performances in said child threads back onto said timing graph.
2. The method as recited in claim 1 , wherein said TSGR further comprising a plurality of replica elements with a correspondence to elements of said sub-graph of said timing graph, said elements comprising nodes and edges.
3. The method as recited in claim 2 , wherein said correspondence is represented by a pointer to an element of said timing graph stored with each of said plurality of replica elements and a map for said TSGR for finding a one of said plurality of replica elements corresponding to a given one of said elements of said sub-graph of said timing graph.
4. The method as recited in claim 3 , wherein said identifying a sub-graph on which a timing analysis task is to be performed comprises identifying at least one element of said timing graph for which a replica element in said TSGR is created, and at least one selection criterion for determining other elements of said timing graph for creating said replica elements.
5. The method as recited in claim 4 , wherein said at least one element is a timing test segment.
6. The method as recited in claim 4 , wherein said at least one selection criterion is applied to edges.
7. The method as recited in claim 4 , wherein said at least one selection criterion is applied to nodes adjacent to nodes already selected for inclusion in said sub-graph.
8. The method as recited in claim 4 , wherein said at least one selection criterion is applied to nodes adjacent to nodes already selected for inclusion in said sub-graph.
9. The method as recited in claim 4 , wherein said creating said TSGR further comprises applying said selection criterion to one or more incoming and outgoing edges of each replica node added to said TSGR.
10. The method as recited in claim 4 , wherein said TSGR and said timing graph are implemented with same data structures.
11. The method as recited in claim 4 , wherein said at least one property associated with at least one set of elements of said timing graph and all said elements of said TSGRs associated thereto, each of said at least one properties consisting of: i. private TSGR properties that are accessed without locking only from elements of one of said TSGRs; ii. public read-only properties accessible without locking, for reading only, from said timing graph or any of said TSGRs; and iii. public updatable properties that are accessible with locking, for reading or writing, from said timing graph or anyone of said TSGRs.
12. The method as recited in claim 1 , wherein said assignment of said timing tasks to said child threads is performed by said parent computation thread.
13. The method as recited in claim 1 , wherein said assignment of said timing tasks to said child threads comprises: i. placing said timing tasks in a work queue by said parent computation thread, and ii. receiving said timing tasks from said work queue by said child threads.
14. The method as recited in claim 1 , wherein said creating said TSGR is performed without locking.
15. The method as recited in claim 1 , wherein each of said TSGRs is only accessed by one of said created child threads.
16. The method as recited in claim 1 , wherein said timing analysis tasks perform a common path pessimism removal (CPPR).
17. The method as recited in claim 1 , wherein said timing analysis tasks comprise critical path reporting.
18. The method as recited in claim 1 , wherein said timing analysis tasks are performed using statistical timing quantities.
19. The method as recited in claim 1 , wherein access locks transfer results back onto said timing graph, in combination with results of said timing analysis task performances in said child threads.
20. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for efficiently performing a multithreaded analysis of a timing graph of a circuit, said method steps comprising: a. using a computer, identifying a plurality of timing analysis tasks comprising performing a common path pessimism removal and computing critical paths for timing reports and identifying associated sub-graphs of said timing graph of said circuit upon which each timing analysis task is to be performed; b. creating a plurality of child computational threads and assigning thereto at least one of said identified timing analysis tasks; c. creating in each of said plurality of child threads a thread-specific graph replica (TSGR) of said associated sub-graph of said timing graph of said circuit on which said at least one timing analysis task assigned thereto is to be performed; d. performing in each child thread said at least one timing analysis task assigned thereto, wherein all timing data generated and stored in said performance is stored in said TSGR of said associated sub-graph of said timing graph; and e. transferring results from each of said timing analysis task performances in said child threads back onto said timing graph.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 2, 2011
February 19, 2013
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