Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device, comprising: a plurality of memory strings each having a plurality of electrically rewritable memory transistors connected in series; and a control circuit for controlling the memory strings, each of the memory strings comprising: a semiconductor layer including a columnar portion that extends in a perpendicular direction to a substrate and functioning as a body of the memory transistors; a charge storage layer formed around a side surface of the columnar portion and configured to enable storage of a charge; and a plurality of first conductive layers formed around the side surface of the columnar portion and the charge storage layer and functioning as gates of the memory transistors, the control circuit comprising: a plurality of second conductive layers formed in the same layers as the plurality of first conductive layers; an insulating layer formed penetrating the plurality of second conductive layers in the perpendicular direction; and a plurality of plug layers formed penetrating the insulating layer in the perpendicular direction, the insulating layer having a rectangular shaped cross-section with a constricted portion in a horizontal direction to the substrate, and the constricted portion being positioned on a long side of the cross-section.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein the plurality of plug layers are disposed in a position other than the vicinity of a line connecting the constricted portions.

3. The nonvolatile semiconductor memory device according to claim 1 , wherein two of the plug layers are each formed such that the distance from one of the two long sides of the cross-section is equal to that from the other.

4. The nonvolatile semiconductor memory device according to claim 1 , wherein two of the plug layers are each formed at a position between a short side of the cross-section and the constricted portion.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein the plurality of plug layers are disposed in alignment in a direction parallel to the long side of the cross-section and in alignment in a direction parallel to a short side of the cross-section.

6. The nonvolatile semiconductor memory device according to claim 1 , wherein the constricted portion is formed in a midpoint vicinity of the long side of the cross-section.

7. The nonvolatile semiconductor memory device according to claim 1 , wherein a plurality of the constricted portions are formed for one cross-section.

8. The nonvolatile semiconductor memory device according to claim 7 , wherein a pair of constricted portions are formed in alignment in a direction parallel to a short side of the cross-section.

9. The nonvolatile semiconductor memory device according to claim 1 , wherein the constricted portion has a triangular shape.

10. The nonvolatile semiconductor memory device according to claim 1 , wherein the constricted portion has a rectangular shape.

11. The nonvolatile semiconductor memory device according to claim 1 , wherein the constricted portion has a semicircular shape.

12. The nonvolatile semiconductor memory device according to claim 1 , wherein the semiconductor layer comprises a joining portion configured to join lower ends of a pair of the columnar portions.