The present invention provides a magnetic memory device capable of providing high-speed access without increasing an array area. Gate word lines are respectively linearly disposed between source impurity regions and drain impurity regions within a memory cell array area. Gate word line protrusions are respectively provided at boundary regions of memory cell forming regions. Contacts relative to the gate word line protrusions are respectively provided at boundary regions of memory cells at adjacent columns. The drain impurity regions are respectively disposed with being shifted from the centers of the memory cell forming regions in such a manner that spaces between the drain impurity regions become large in the regions in which the protrusions are disposed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A magnetic memory device comprising: a memory array in which a plurality of MRAM cells arranged in matrix form and each having a series body of a variable magnetoresistive element and a selection transistor are disposed; a plurality of word lines disposed corresponding to rows of the MRAM cells and coupled with gates of the selection transistors of the MRAM cells of the corresponding rows respectively; a plurality of bit lines disposed corresponding to columns of the MRAM cells and respectively coupled to the selection transistors of the MRAM cells of the corresponding columns; and a shape dummy cell area disposed around the memory array and provided with a plurality of shape dummy cells each of which at least has an element of the same shape as the variable magnetoresistive element of the MRAM cell and which are disposed in alignment with the MRAM cells, wherein the shape dummy cell area has a first shape dummy area in which each first shape dummy cell of the same structure as the MRAM cell, having a variable magnetoresistive element and a selection transistor is disposed, a second shape dummy area which is disposed at an outer periphery of the first shape dummy area and in which a second shape dummy cell having a dummy magnetoresistive element of the same structure as the variable magnetoresistive element of the MRAM cell is disposed, and a third shape dummy area which is disposed at an outer periphery of the second shape dummy area and in which a third shape dummy cell having a dummy magnetoresistive element of the same structure as the variable magnetoresistive element is disposed, wherein at the second shape dummy area, an element for applying a bias voltage to a substrate region of the memory array is disposed in a region below the dummy magnetoresistive element, and wherein at the third shape dummy area, a transistor of a peripheral circuit for obtaining access to the memory array is disposed in a lower region of the dummy magnetoresistive element.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 8, 2012
March 5, 2013
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