Digital silicon photomultiplier for TOF-PET

1. A detector pixel comprising: a trigger line; a digital data bus; a plurality of detector cells, each detector cell including: a photodiode biased in a breakdown region, digital circuitry coupled with the photodiode, the trigger line, and the digital data bus, the digital circuitry being configured to output a first digital value in a quiescent state and a second digital value responsive to detection of a photon by the photodiode, quenching circuitry configured to transition the detector cell back to the quiescent state after detection of a photon by the photodiode; digital triggering circuitry connected to the trigger line and configured to start an integration time period responsive to a selected number of one or more of the detector cells transitioning from the first digital value to the second digital value; and pixel level readout digital circuitry connected to the digital data bus that accumulates a digital count of a total number of transitions of the plurality of detector cells from outputting the first digital value to outputting the second digital value accumulated over the integration time period started by digital triggering circuitry.

2. The detector pixel as set forth in claim 1 , wherein each detector cell includes: a buffer that buffers the second digital values, the pixel level readout digital circuitry being configured to sequentially read the buffers associated with each of the detector cells having the second digital value over the digital data bus to produce the digital count.

3. The detector pixel as set forth in claim 1 , wherein each detector cell is associated with an accumulator, each accumulator being configured to accumulate transitions of the associated detector cell from outputting the first digital value to outputting the second digital value over the integration time period, the pixel level readout digital circuitry summing the values stored in the accumulators at the end of the integration time period to produce the count.

4. The detector pixel as set forth in claim 1 , wherein the digital triggering circuitry accesses a reference clock and determines a digital timestamp associated with the count.

5. The detector pixel as set forth in claim 1 , wherein the digital triggering circuitry is configured to start the integration time period responsive to a single detector cell transitioning from the first digital value to the second digital value.

6. The detector pixel as set forth in claim 1 , wherein the digital triggering circuitry is configured to validate the trigger signal responsive to two of the detector cells transitioning from the first digital value to the second digital value in a selected time window.

7. The detector pixel as set forth in claim 1 , further comprising: a scintillator that converts a radiation particle to a burst of light, the plurality of detector cells being arranged to detect the burst of light, the integration time period corresponding to an acquisition interval for the burst of light.

8. The detector pixel as set forth in claim 1 , wherein the pixel level readout digital circuitry dynamically determines the integration time period based on when a rate of new switching events decreases below a threshold value.

9. The detector pixel as set forth in claim 1 , further including: trigger validation circuitry which detects false trigger signals.

10. The detector pixel as set forth in claim 1 , further including: a trigger validation circuitry which aborts an integration time period in response to not receiving additional second digital value within a selected time window.

11. The detector pixel as set forth in claim 1 , wherein the digital triggering circuitry includes: digital time stamp circuitry which receives a clock signal and the trigger signal and outputs a time stamp responsive to each trigger signal indicative of a time at which each trigger signal occurs.

12. The detector pixel as set forth in claim 1 , wherein the integration time period is started in response to the first digital value output from one of the plurality of detector cells.

13. A detector pixel including: an array of detector cells, each detector cell including a photodiode biased in a breakdown region and digital circuitry coupled with the photodiode, the digital circuitry being configured to output a first digital value in a quiescent state and a second digital value responsive to detection of a photon by the photodiode; digital triggering circuitry configured to output a trigger signal indicative of a start of an integration time period responsive to a selected number of one or more of the detector cells transitioning from the first digital value to the second digital value; readout digital circuitry that accumulates a digital count of the total number of transitions of detector cells of the array of detector cells from outputting the first digital value to outputting the second digital value accumulated over the integration time period; and trigger validation circuitry that monitors a current in the detector pixel and aborts the accumulation of the count responsive to the monitored current and an abort criterion.

14. The detector pixel as set forth in claim 13 , wherein each detector cell further includes: quenching circuitry configured to transition the detector cell back to the quiescent state after detection of a photon by the photodiode.

15. A radiation detector for detecting radiation events comprising: an array of detector pixels, each detector pixel including: a plurality of detector cells, each detector cell including a photodiode biased in a breakdown region and digital circuitry coupled with the photodiode, the digital circuitry being configured to output a first digital value in a quiescent state and a second digital value responsive to detection of a photon by the photodiode, digital triggering circuitry configured to output a trigger signal indicative of a start of an integration time period responsive to a selected number of one or more of the detector cells transitioning from the first digital value to the second digital value, the integration time period being dynamically terminated based on when a rate of transitions decreases below a threshold value, and readout digital circuitry that accumulates a digital count of a total number of transitions of the photodiodes of the plurality of detector cells accumulated over the integration time period.

16. A radiation detector pixel comprising: a scintillator which generates a burst of light in response to a radiation event; an array of detector cells, each detector cell including: an avalanche photodiode which transitions from a quiescent state to a current emitting state in response to light, a quenching circuit which returns the avalanche photodiode to the quiescent state each time the avalanche photodiode transitions to the current emitting state, a digital circuit that outputs a count each time the avalanche photodiode transitions to the current emitting state, a counter which accumulates the counts, a trigger driver which sends out a trigger signal in response to at least one count; a trigger line connected with the trigger drivers of each detector cell to start the counter accumulating the counts over an integration period in response to the trigger signal; a readout circuit which, at an end of the integration period, reads out the counts and integrates the read out counts from the counters to generate a total count.

17. A radiation detector including a plurality of the detector pixels as set forth in claim 16 on a common substrate and of CMOS circuitry.

18. The radiation detector pixel as set forth in claim 16 , wherein the integration time period is terminated in response to detection of an end of the burst of light.