In the case of tracing processor activity and generating data streams multiple triggers can be generated at the same time. The issue is further complicated in a protected pipeline where certain locations are considered as in illegal instruction boundary. During those cycles certain information is invalid and cannot be transmitted to the user. Thus a received trace trigger cannot begin. This invention resolves all ambiguities related to multiple triggers so that the user has a known predictable behavior based on the setup of the triggers.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of tracing data processor operation comprising the steps of: upon receipt of a trace start trigger and a trace end trigger during delay slot cycles of a branch instruction if trace collection is OFF and no trace trigger occurs at the branch destination, turning trace collection ON for the duration of said delay slot and thereafter turning trace collection OFF, and if trace collection is ON and no trace trigger occurs at the branch destination, turning trace collection OFF after said delay slot, if a trace start trigger occurs at the branch destination, turning trace collection ON at the branch destination or continuing trace collection ON, if trace collection is OFF and a trace end trigger occurs at the branch destination, turning trace collection ON for the duration of the branch destination instruction and then turning trace collection OFF, and if trace collection is ON and a trace end trigger occurs at the branch destination, turning trace collection OFF after the branch destination instruction.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 22, 2002
March 19, 2013
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