In a memory device, an array of memory cells is coupled between a virtual ground node and a supply node. First and second transistors are coupled in source-drain parallel between the virtual ground node and a ground bus. The first transistor is substantially larger than the second transistor. A control circuit provides a first gate signal to a gate of the first transistor and a second gate signal to a gate of the second transistor. The control circuit includes: a configuration memory cell providing a first control signal; an interconnect providing a second control signal; and control logic receiving the first and second control signals and providing the first gate signal. The array of memory cells has three modes responsive to the first and second gate signals, where the three modes include an active mode, a first sleep mode, and a second sleep mode.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: an array of memory cells coupled between a virtual ground node and a supply node; a first transistor and a second transistor coupled in source-drain parallel to one another between the virtual ground node and a ground bus; wherein the first transistor is substantially larger than the second transistor; a control circuit coupled to provide a first gate signal to a gate of the first transistor and further coupled to provide a second gate signal to a gate of the second transistor; wherein the control circuit includes: a first configuration memory cell coupled to provide a first control signal; an interconnect coupled to provide a second control signal; and first control logic coupled to receive the first control signal and the second control signal, and further coupled to provide the first gate signal; and wherein the array of memory cells has three modes responsive to the first gate signal and the second gate signal, the three modes including an active mode, a first sleep mode, and a second sleep mode.
2. The memory device according to claim 1 , wherein: the first sleep mode electrically decouples the array of memory cells from the ground bus; and the second sleep mode electrically couples the array of memory cells to the ground bus through a resistance provided with the second transistor, the resistance being small enough to retain data stored in the array of memory cells.
3. The memory device according to claim 2 , wherein the control circuit further includes: a second configuration memory cell coupled to provide a third control signal; and a multiplexer coupled to receive the first control signal and the third control signal, and further coupled to select the second gate signal responsive to a fourth control signal provided from the interconnect.
4. The memory device according to claim 3 , wherein: the first configuration memory cell and the second configuration memory cell are user programmable cells; and the first configuration memory cell and the second configuration memory cell have outputs for directly driving logic signal states.
5. The memory device according to claim 1 , wherein: the array of memory cells comprises a block random access memory; and the interconnect comprises a user programmable interconnect.
6. The memory device according to claim 1 , wherein the array of memory cells comprises an array of static random access memory cells.
7. The memory device according to claim 1 , wherein an output of the first configuration memory cell is directly coupled to the gate of the second transistor, wherein the first control signal and the second gate signal are the same signal.
8. The memory device according to claim 1 , wherein the control circuit further includes: a first non-volatile memory cell coupled to provide a third control signal; and second control logic coupled to receive the third control signal and the first control signal and further coupled to provide the second gate signal.
9. The memory device according to claim 8 , further comprising: a third transistor coupled in source-drain parallel with the first transistor and the second transistor between the virtual ground node and a ground bus; wherein the first transistor is substantially larger than each of the second transistor and the third transistor; wherein the control circuit is coupled to provide a third gate signal to a gate of the third transistor; and wherein the control circuit further includes: a second non-volatile memory cell coupled to provide a fourth control signal; and third control logic coupled to receive the fourth control signal and the first control signal, and further coupled to provide the third gate signal.
10. The memory device according to claim 9 , wherein: the second transistor and the third transistor are a same size; and each of the first control logic, the second control logic, and the third control logic comprises a respective AND gate.
11. A memory device, comprising: an array of memory cells coupled between a virtual ground node and a supply node; a first transistor and a second transistor coupled in source-drain parallel to one another between the virtual ground node and a ground bus; wherein the first transistor is substantially larger than the second transistor; a control circuit coupled to provide a first gate signal to a gate of the first transistor, and further coupled to provide a second gate signal to a gate of the second transistor; wherein the control circuit includes: a first configuration memory cell coupled to provide a first control signal; an interconnect coupled to provide a second control signal; first control logic coupled to receive the first control signal and the second control signal, and further coupled to provide the first gate signal; a second configuration memory cell coupled to provide a third control signal; a first non-volatile memory cell coupled to provide a fourth control signal; and second control logic coupled to receive the third control signal and the fourth control signal to provide the second gate signal; and wherein the array of memory cells has three modes responsive to the first gate signal and the second gate signal, the three modes including an active mode, a first sleep mode, and a second sleep mode.
12. The memory device according to claim 11 , wherein: the first sleep mode electrically decouples the array of memory cells from the ground bus; and the second sleep mode electrically couples the array of memory cells to the ground bus through a resistance provided with the second transistor, the resistance being small enough to retain data stored in the array of memory cells.
13. The memory device according to claim 11 , further comprising: a third transistor coupled in source-drain parallel with the first transistor and the second transistor between the virtual ground node and a ground bus; wherein the first transistor is substantially larger than each of the second transistor and the third transistor; wherein the control circuit is coupled to provide a third gate signal to a gate of the third transistor; and wherein the control circuit further includes: a third configuration memory cell coupled to provide a fifth control signal; a second non-volatile memory cell coupled to provide a sixth control signal; and third control logic coupled to receive the fifth control signal and the sixth control signal, and further coupled to provide the third gate signal.
14. The memory device according to claim 13 , wherein: the third transistor is smaller than the second transistor; and each of the first control logic, the second control logic, and the third control logic comprises a respective AND gate.
15. The memory device according to claim 11 , wherein the array of memory cells comprises an array of static random access memory cells.
16. The memory device according to claim 11 , wherein: the interconnect comprises a user programmable interconnect; and the array of memory cells comprises a block random access memory.
17. An integrated circuit, comprising: an array of memory cells; a first transistor and a second transistor coupled in source-drain parallel to one another between the array of memory cells and a ground; wherein the first transistor is substantially larger than the second transistor; and a control circuit having a first output coupled to a gate of the first transistor and a second output coupled to a gate of the second transistor; wherein the control circuit includes: a configuration memory cell having an output; wherein the output of the configuration memory cell is coupled to the gate of the second transistor; an interconnect having an output; and control logic having a first input coupled to the output of the configuration memory cell, a second input coupled to the output of the interconnect, and an output coupled to the first output of the control circuit.
18. The integrated circuit according to claim 17 , wherein the array of memory cells has three modes responsive to signals on the first and second outputs of the control circuit, the three modes including an active mode, a first sleep mode, and a second sleep mode.
19. The integrated circuit according to claim 18 , wherein: the first sleep mode electrically decouples the array of memory cells from the ground; and the second sleep mode electrically couples the array of memory cells to the ground bus through a resistance provided with the second transistor, the resistance being small enough to retain data stored in the array of memory cells.
20. The integrated circuit according to claim 17 , wherein the control logic comprises an AND gate.
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April 21, 2011
April 2, 2013
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