A GaN related compound semiconductor element includes: a channel layer made of a GaN related compound semiconductor; and a source layer and a drain layer, which are disposed in a manner of sandwiching the channel layer. The source layer includes two adjacent ridge portions which are formed by selective growth. A source electrode is formed over the surface, sandwiched by the ridge portions, of the channel layer, and the surfaces of the respective two adjacent ridge portions. The selective-growth mask formed between the two ridge portions is removed by wet etching. In addition, as another embodiment, a gate electrode is formed in a manner that the direction of the longer dimension of the gate electrode is aligned with the m plane of the channel layer. Moreover, as still another embodiment, the channel layer has a multilayer structure in which a GaN layer doped with no impurity is used as an intermediate layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A GaN related compound semiconductor element comprising: a channel layer made of a GaN related compound semiconductor; a source layer including two adjacent ridge portions formed therein by selective growth; a drain layer; wherein; the channel layer is sandwiched by the source layer and the drain layer, and two selective-growth masks are left on the channel layer surface located outside of the two adjacent ridge portions and removed from a portion of the channel layer located between the two adjacent ridge portions after being used for the selective growth and formed in a manner of sandwiching the two adjacent ridge portions; two gate electrodes are provided on the two selective-growth masks and formed in a manner of sandwiching the two adjacent ridge portions.
2. The GaN related compound semiconductor device comprising the GaN related compound semiconductor element according to claim 1 .
3. The GaN related compound semiconductor element of claim 1 , wherein a groove portion is formed to extend from the channel layer to the drain layer so that the drain layer is partially exposed to the outside; and an insulating film is deposited from the channel layer to the drain layer in the groove; and a drain electrode is formed on the exposed part and on a part of the insulating film.
4. The GaN related compound semiconductor element of claim 1 , wherein a source electrode is formed on top and adjacent to side surfaces of the two adjacent ridge portions and above the portion of the channel layer located between the ridges.
5. The GaN related compound semiconductor element of claim 1 , wherein the two selective growth masks and the source layer are disposed on the same plane of the channel layer which is formed flat.
6. The GaN related compound semiconductor element of claim 1 , wherein the two gate electrodes are formed in a manner that each short side of the two gate electrodes is aligned with a normal direction to the m crystal plane of the channel layer and each long side of the two gate electrodes are aligned with the m crystal plane of the channel layer.
7. The GaN related compound semiconductor element of claim 1 , wherein the channel layer has a multilayer structure including an undoped GaN related layer in a middle portion thereof.
8. The GaN related compound semiconductor element of claim 7 , wherein the undoped GaN related layer is formed of any one of an undoped GaN layer and an undoped A 1 GaN layer.
9. The GaN related compound semiconductor element of claim 7 , wherein an electrode is in contact with a GaN layer of the multilayer channel layer.
10. The GaN related compound semiconductor element of claim 9 , wherein the channel layer includes an AIGaN layer doped with an impurity.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 13, 2007
April 16, 2013
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