A semiconductor device includes an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a multilayer body including a plurality of first interconnect layers formed in a plurality of insulating films stacked between the semiconductor substrate and the connecting portion and including an upper interconnect connected to the connecting portion, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit. The multilayer body is connected to the ring body by at least one of the plurality of first interconnect layers. The lead line is connected to the ring body.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a plurality of insulating films stacked between the semiconductor substrate and the connecting portion; a protective film formed on the plurality of insulating films, and having an opening; a multilayer body including a plurality of first interconnect layers formed in the plurality of insulating films and including an upper interconnect connected to the electrode pad in the opening of the protective film, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit, wherein the upper interconnect has a larger width than the opening of the protective film, the multilayer body is electrically connected to the ring body, the lead line is connected to the ring body, and one of the plurality of first interconnect layers is directly connected to one of the plurality of the second interconnect layers.
2. The semiconductor device of claim 1 , wherein the lead line is a power supply line, and is connected to an upper interconnect of the plurality of second interconnect layers.
3. The semiconductor device of claim 1 , wherein the plurality of first interconnect layers include an interconnect arranged in a form extending in a direction toward the internal circuit.
4. The semiconductor device of claim 3 , wherein the one of the plurality of first interconnect layers connected to the ring body is an interconnect being the third layer under the connecting portion.
5. The semiconductor device of claim 1 , wherein the plurality of first interconnect layers include an interconnect arranged in a form extending in a direction parallel to an end surface of the semiconductor substrate closest to the electrode pad.
6. The semiconductor device of claim 1 , wherein the plurality of first interconnect layers includes a first interconnect arranged in a form extending in a direction toward the internal circuit, and a second interconnect arranged in a form extending in a direction parallel to an end surface of the semiconductor substrate closest to the electrode pad, and the second interconnect is provided lower than the first interconnect.
7. The semiconductor device of claim 1 , wherein an upper interconnect of the plurality of second interconnect layers has a larger width than a lower interconnect of the plurality of second interconnect layers.
8. The semiconductor device of claim 1 , wherein an outer peripheral surface of an upper interconnect of the plurality of second interconnect layers is located outside an outer peripheral surface of a lower interconnect.
9. The semiconductor device of claim 1 , wherein the at least one line via includes an upper line via and a lower line via, and the upper line via has a larger width than the lower line via.
10. The semiconductor device of claim 1 , wherein the at least one line via includes an upper line via and a plurality of lower line vias, and the plurality of lower line vias are formed along each other.
11. The semiconductor device of claim 1 , wherein a plurality of lower interconnects of the plurality of second interconnect layers are formed along each other.
12. The semiconductor device of claim 1 , wherein the plurality of insulating films have different dielectric constants, and an upper insulating film has a higher dielectric constant than a lower insulating film.
13. The semiconductor device of claim 1 , wherein part of the plurality of insulating films is formed between the lead line and the upper interconnect connected to the electrode pad.
14. The semiconductor device of claim 1 , wherein one of the plurality of second interconnect layers, which is formed in a same layer as the lead line, is formed without interposing space.
15. The semiconductor device of claim 1 , wherein the upper interconnect connected to the electrode pad is continuously surrounded by one of the plurality of second interconnect layers formed in a same layer as the upper interconnect.
16. The semiconductor device of claim 15 , wherein the upper interconnect connected to the electrode pad, and the interconnect of the plurality of second interconnect layers formed in the same layer as the upper interconnect are separated by part of the plurality of insulating films.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 22, 2010
April 16, 2013
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.