Patentable/Patents/US-8426257
US-8426257

Method for fabricating semiconductor device

PublishedApril 23, 2013
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing repair-etching such that part of the insulation layer remains above the fuse.

Patent Claims
7 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for fabricating a semiconductor device, the method comprising: forming a substrate having a cell region and a fuse region; forming a metal interconnection in the cell region and a fuse in the fuse region, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, wherein the metal interconnection has the same structure with the fuse and is concurrently formed with the fuse; completely removing the anti-reflective layer and simultaneous etching a portion of the metal layer to expose an upper portion of the etched metal layer, thereby forming a resultant structure, wherein the anti-reflective layer and the portion of the metal layer are etched using a gas mixture of chlorine (Cl 2 ), trichloroborane (BCl 3 ), argon (Ar), nitrogen (N 2 ) and fluoroform (CHF 3 ); forming an insulation layer over a whole surface of the resultant structure including the fuse; and performing a repair-etching such that part of the insulation layer remains above the fuse, wherein the anti-reflective layer includes any one of a single-layered structure of any one selected from a Ti layer, a TiN layer, and a silicon oxynitride (SiON) layer, and a stacked structure of the Ti layer, a TiN layer, and a SiON layer.

2

2. The method of claim 1 , wherein the barrier layer is one selected from a single-layered structure of a titanium (Ti) layer or a titanium nitride (TiN) layer, a stacked structure of the Ti layer and the TiN layer, and a stacked structure of the Ti layer, the Ti layer, and the TiN layer.

3

3. The method of claim 1 , wherein the metal layer includes aluminum (Al).

4

4. The method of claim 1 , wherein the gas of Cl 2 is used in an amount from approximately 30 sccm to approximately 200 sccm, the gas of BCl 3 is used in an amount from approximately 30 sccm to approximately 200 sccm, the gas of Ar is used in an amount from approximately 30 sccm to approximately 150 sccm, the gas of N 2 is used in an amount from approximately 1 sccm to approximately 20 sccm, and the gas of CHF 3 is used in an amount from approximately 15 sccm to approximately 150 sccm.

5

5. The method of claim 1 , wherein the anti-reflective layer and the portion of the metal layer are etched by applying a pressure from approximately 7 mT to approximately 20 mT, a top power from approximately 400 W to approximately 1,000 W, and a bottom power from approximately 50 W to approximately 200 W.

6

6. The method of claim 1 , wherein the portion of the metal layer is etched at a thickness from approximately 500 Å to approximately 3,000 Å.

7

7. The method of claim 1 , wherein the insulation layer includes an oxide layer.

Classification Codes (CPC)

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Patent Metadata

Filing Date

December 20, 2007

Publication Date

April 23, 2013

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