Determining a schedule of instructions for an integrated circuit graphics pipeline. The method includes accessing a state of a host system. The state comprises operations to be performed on fragments to be processed by the graphics pipeline. The method further includes determining a vector based on the state and indexing a table based on the vector to obtain a predetermined listing and ordering of macro-operations to be executed. The method still further includes determining instructions for programming the graphics pipeline based the executing of the macro-operations in the scheduled order.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of determining a schedule of instructions for a graphics pipeline, said method comprising: accessing a state of a host system; determining a vector based on said state, wherein said vector comprises information about said state; indexing a table based on said vector to obtain a plurality of macro-operations associated with said state, wherein said plurality of macro-operations are associated with at least one operation to be performed by said graphics pipeline; and determining at least one instruction for programming said graphics pipeline to implement said state, wherein said at least one instruction is determined based on said plurality of macro-operations and also based on context information, wherein said context information comprises data associated with graphics processing that is used to perform said at least one operation.
2. The method of claim 1 , wherein said at least one operation is selected from a group consisting of a texture operation, an alpha test operation, a stencil operation, a fog operation, an anti-alias operation, a depth test operation, an alpha test, a color mask operation, a blending operation, and a pass-through operation.
3. The method of claim 1 , wherein said at least one other operation is selected from a group consisting of a multiply operation and an add operation.
4. The method of claim 1 , wherein said context information further identifies data accessed as part of performing said at least one operation.
5. The method of claim 4 , wherein said data comprises a texture map.
6. The method of claim 1 , wherein said determining at least one instruction further comprises executing at least one module to generate said at least one instruction.
7. The method of claim 6 further comprising: determining an order of execution of said at least one module based on an ordering of said plurality of macro-operations, and wherein said determining at least one instruction further comprises executing said at least one module in said order of execution to generate said at least one instruction.
8. The method of claim 6 , wherein said at least one module is selected from a group consisting of a texture module, an alpha test module, a fog module, an anti-alias module, a depth test module, and a color mask module.
9. The method of claim 1 , wherein said state comprises at least one enable flag associated with said at least one operation.
10. The method of claim 1 , wherein said state is substantially compliant with an OpenGL graphics state.
11. The method of claim 1 , wherein said method is implemented by a device driver of said host system.
12. The method of claim 1 , wherein said graphics pipeline comprises at least one unit selected from a group consisting of an arithmetic logic unit, a setup unit, a raster unit, a gatekeeper unit, a data fetch unit, and a data write unit.
13. The method of claim 1 further comprising: programming said graphics pipeline based on said at least one instruction.
14. A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a method of determining a schedule of instructions for a graphics pipeline, said method comprising: accessing a state of a host system; determining a vector based on said state, wherein said vector comprises information about said state; indexing a table based on said vector to obtain a plurality of macro-operations associated with said state, wherein said plurality of macro-operations are associated with at least one operation to be performed by said graphics pipeline; and determining at least one instruction for programming said graphics pipeline to implement said state, wherein said at least one instruction is determined based on said plurality of macro-operations and also based on context information, wherein said context information comprises data associated with graphics processing that is used to perform said at least one operation.
15. The computer-readable memory of claim 14 , wherein said at least one operation is selected from a group consisting of a texture operation, an alpha test operation, a stencil operation, a fog operation, an anti-alias operation, a depth test operation, an alpha test, a color mask operation, a blending operation, and a pass-through operation.
16. The computer-readable memory of claim 14 , wherein said at least one other operation is selected from a group consisting of a multiply operation and an add operation.
17. The computer-readable memory of claim 14 , wherein said context information further identifies data accessed as part of performing said at least one operation.
18. The computer-readable memory of claim 17 , wherein said data comprises a texture map.
19. The computer-readable memory of claim 14 , wherein said determining at least one instruction further comprises executing at least one module to generate said at least one instruction.
20. The computer-readable memory of claim 19 , wherein said method further comprises: determining an order of execution of said at least one module based on an ordering of said plurality of macro-operations, and wherein said determining at least one instruction further comprises executing said at least one module in said order of execution to generate said at least one instruction.
21. The computer-readable memory of claim 19 , wherein said at least one module is selected from a group consisting of a texture module, an alpha test module, a fog module, an anti-alias module, a depth test module, and a color mask module.
22. The computer-readable memory of claim 14 , wherein said state comprises at least one enable flag associated with said at least one operation.
23. The computer-readable memory of claim 14 , wherein said state is substantially compliant with an OpenGL graphics state.
24. The computer-readable memory of claim 14 , wherein said method is implemented by a device driver of said host system.
25. The computer-readable memory of claim 14 , wherein said graphics pipeline comprises at least one unit selected from a group consisting of an arithmetic logic unit, a setup unit, a raster unit, a gatekeeper unit, a data fetch unit, and a data write unit.
26. The computer-readable memory of claim 14 , wherein said method further comprises: programming said graphics pipeline based on said at least one instruction.
27. A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said system implement a method of determining a schedule of instructions for a graphics pipeline, said method comprising: accessing a state of a host system; determining a vector based on said state, wherein said vector comprises information about said state; indexing a table based on said vector to obtain a plurality of macro-operations associated with said state, wherein said plurality of macro-operations are associated with at least one operation to be performed by said graphics pipeline; and determining at least one instruction for programming said graphics pipeline to implement said state, wherein said at least one instruction is determined based on said plurality of macro-operations and also based on context information, wherein said context information comprises data associated with graphics processing that is used to perform said at least one operation.
28. The system of claim 27 , wherein said at least one operation is selected from a group consisting of a texture operation, an alpha test operation, a stencil operation, a fog operation, an anti-alias operation, a depth test operation, an alpha test, a color mask operation, a blending operation, and a pass-through operation.
29. The system of claim 27 , wherein said at least one other operation is selected from a group consisting of a multiply operation and an add operation.
30. The system of claim 27 , wherein said context information further identifies data accessed as part of performing said at least one operation.
31. The system of claim 30 , wherein said data comprises a texture map.
32. The system of claim 27 , wherein said determining at least one instruction further comprises executing at least one module to generate said at least one instruction.
33. The system of claim 32 , wherein said method further comprises: determining an order of execution of said at least one module based on an ordering of said plurality of macro-operations, and wherein said determining at least one instruction further comprises executing said at least one module in said order of execution to generate said at least one instruction.
34. The system of claim 32 , wherein said at least one module is selected from a group consisting of a texture module, an alpha test module, a fog module, an anti-alias module, a depth test module, and a color mask module.
35. The system of claim 27 , wherein said state comprises at least one enable flag associated with said at least one operation.
36. The system of claim 27 , wherein said state is substantially compliant with an OpenGL graphics state.
37. The system of claim 27 , wherein said method is implemented by a device driver of said host system.
38. The system of claim 27 , wherein said graphics pipeline comprises at least one unit selected from a group consisting of an arithmetic logic unit, a setup unit, a raster unit, a gatekeeper unit, a data fetch unit, and a data write unit.
39. The system of claim 27 , wherein said method further comprises: programming said graphics pipeline based on said at least one instruction.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 14, 2004
April 23, 2013
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.