A method to test and package dies so as to increase overall yield is provided. The method includes performing a wafer test on a first die and mounting the first die on a package substrate to form a partial package, if the wafer test of the first die is successful. The method further includes performing a system test on the partial package including the first die and stacking a second die on the first die if the system test on the partial package and the first die is successful.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, comprising: mounting a first die on a package substrate, to form a partial package if a wafer test of the first die is successful, wherein the partial package requires one or more additional dies to be mounted in order to form a complete package; performing a system test on the partial package, wherein performing the system test comprises performing a performance and power characteristic test on the partial package; determining if the partial package is functional as a system, wherein the partial package is functional when the system test yields a set of results that meet predetermined thresholds; and based on determining the partial package is functional as a system, mounting a second die on the first die, otherwise discarding the partial package.
2. The method of claim 1 , further comprising performing a system test on a partial package including both the first and second dies.
3. The method of claim 1 , further comprising performing a system test on a complete package including both the first and second dies.
4. The method of claim 1 , further comprising: stacking a third die on the second die using one or both of die-to-die vias and through-silicon-vias.
5. The method of claim 1 , further comprising: creating at least one of die-to-die vias or through-silicon-vias (TSVs) on the first and/or second die prior to the stacking step.
6. The method of claim 5 farther comprising: filling the through-silicon-vias with copper or tungsten prior to the stacking step.
7. The method of claim 6 , the stacking step further comprising: stacking the second die on the first die using one or both of the die-to-die vias or the through-silicon-vias.
8. The method of claim 1 , the stacking step further comprising: stacking the second die on the first die using micro-bumps on the second die.
9. The method of claim 1 , wherein the first die is a central processing unit or a graphics processing unit.
10. The method of claim 1 , wherein the second die is a memory die.
11. The method of claim 1 , further comprising: creating process devices and vias on the first and second dies prior to the stacking step.
12. The method of claim 1 , farther comprising: thinning a substrate of the first and/or second die to expose through-silicon-vias prior to the stacking step.
13. The method of claim 1 , wherein the wafer test of the first die is successful if the first die meets or exceeds predetermined thresholds of desired performance requirements.
14. The method of claim 1 , wherein the system test of the partial package and the first die is successful if the partial package and the first die meet or exceed predetermined thresholds of desired performance requirements.
15. The method of claim 1 , wherein the system test on the partial package is conducted using lead connectors of the partial package and wherein the lead connectors are external to the partial package.
16. The method of claim 1 , wherein the system test determines at least one of performance, power, thermal and electrical characteristics of the first die via lead connectors of the package in a simulation of an operating environment of the first die.
17. The method of claim 1 , wherein the system test includes electrical tests to determine whether the first die can pass voltage and frequency specification requirements of an operating environment of the first die.
18. The method of claim 1 , wherein the system test runs an Operating System (OS) on the first die to determine whether the first die is functional.
19. The method of claim 1 , wherein the system test simulates thermal conditions of a computational device, and wherein the computational device is one of a desktop computer, a laptop computer or a cell phone.
20. A method, comprising: creating a first die having die-to-die vias, through-silicon vias, and connector bumps; mounting the first die on a package substrate using the connector bumps to form a partial package, wherein the partial package requires one or more additional dies to be mounted in order to form a complete package; performing a system test on the partial package, wherein performing the system test comprises performing a performance and power characteristic test on the partial package; determining if the partial package is functional as a system, wherein the partial package is functional when the system test yields a set of results that meet predetermined thresholds; and based on determining the partial package is functional as a system, stacking a second die on the first die using at least one of the die-to-die vias and the through-silicon vias.
21. The method of claim 20 , further comprising performing a system test on the partial package including both the first and second dies.
22. The method of claim 20 , further comprising performing a system test on a complete package including both the first and second dies, the complete package including the partial package and a package cover.
23. A method, comprising: mounting a first die on a package substrate to form a partial package if a wafer test of the first die is successful; performing a system test, wherein the system test comprises performing a performance and power characteristic test on the partial package, and the system test runs an Operating System (OS) on the first die to determine whether the first die is functional; and stacking a second die on the first die if the system test on the partial package is successful, wherein the system test on the partial package is successful if it yields a set of results that meet predetermined thresholds.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 2, 2010
May 28, 2013
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