Circuits and methods that use third dimension memory as a different memory technology are described. The third dimension memory can be used for application specific data storage and/or to emulate conventional memory types such as DRAM, FLASH, SRAM, and ROM or new memory types as they become available. A processor-memory system implements a memory operable as different memory technologies. The processor-memory system includes a logic subsystem and a memory subsystem, which includes third dimension memory cells. The logic subsystem implements memory technology-specific signals to interact with the third dimension memory cells as memory cells of a different memory technology. As such, the memory subsystem can emulate different memory technologies. The logic subsystem can be fabricated FEOL on a substrate and the memory subsystem can be fabricated BEOL directly on top of the substrate. An interlayer interconnect structure can electrically couple the logic subsystem with the memory subsystem.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, comprising: a plurality of processors fabricated on a single substrate; and a third dimension memory fabricated directly above and in contact with the single substrate, the third dimension memory is electrically coupled with the plurality of processors and is configured to form different computer readable media for storing executable instructions, wherein at least one of the processors of the plurality of processors is responsive to the executable instructions and is configured to emulate an external port for communicating externally.
2. The integrated circuit of claim 1 , wherein at least a portion of the plurality of processors and the third dimension memory are positioned in a single package.
3. The integrated circuit of claim 1 , wherein the third dimension memory includes memory cells that are vertically stacked in relation to each other without an intervening substrate.
4. The integrated circuit of claim 1 , wherein the external port comprises an input/output (I/O) port.
5. The integrated circuit of claim 4 , wherein the I/O port is a port selected from the group consisting of a USB port, a Gigabit Ethernet port, a SATA port, an eSATA port, an 8B/10B Serializer/Deserializer port, an external DRAM port, an external SDRAM port, and an external FLASH memory port.
6. The integrated circuit of claim 1 , wherein at least one of the processors of the plurality of processors comprises one or more FPGAs.
7. The integrated circuit of claim 1 , wherein the plurality of processors are fabricated front-end-of-the-line (FEOL) on the single substrate and the third dimension memory is fabricated back-end-of-the-line (BEOL) directly above and in contact with the single substrate.
8. An integrated circuit, comprising: a logic subsystem fabricated on a single substrate; and a third dimension memory fabricated directly above and in contact with the single substrate, the third dimension memory is electrically coupled with the logic subsystem and is configured to form different computer readable media for storing executable instructions, wherein the logic subsystem includes a processing device responsive to the executable instructions and is configured to emulate an input/output (I/O) port.
9. The integrated circuit of claim 8 , wherein the I/O port is a port selected from the group consisting of a USB port, a Gigabit Ethernet port, a SATA port, an eSATA port, an 8B/10B Serializer/Deserializer port, an external DRAM port, an external SDRAM port, and an external FLASH memory port.
10. The integrated circuit of claim 8 , wherein at least a portion of the logic subsystem and the third dimension memory are positioned in a single package.
11. The integrated circuit of claim 8 , wherein the third dimension memory includes memory cells that are vertically stacked in relation to each other without an intervening substrate.
12. The integrated circuit of claim 8 , wherein the processing device comprises at least one FPGA.
13. The integrated circuit of claim 8 , wherein the logic subsystem is fabricated front-end-of-the-line (FEOL) on the single substrate and the third dimension memory is fabricated back-end-of-the-line (BEOL) directly above and in contact with the single substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 18, 2009
June 4, 2013
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