A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A microelectronic interconnect element, comprising: a plurality of first metal lines each having a lower surface whose width and length extend within a reference plane, an upper surface remote from the reference plane, and edges extending between the upper and lower surfaces, a first distance between the upper and lower surfaces of such first metal line defining a thickness of such first metal line; a plurality of second metal lines interleaved with the first metal lines in a direction of the width of the first metal lines, each of the second metal lines having an upper surface whose width and length extend within the reference plane and a lower surface remote from the reference plane, a second distance between the upper and lower surfaces of such second metal line defining a thickness of such second metal line; and a dielectric layer separating a metal line of the first metal lines from an adjacent metal line of the second metal lines, wherein a pitch between the first metal line and the second metal line adjacent thereto is smaller than a first pitch between adjacent ones of the first metal lines and is smaller than a second pitch between adjacent ones of the second metal lines, and wherein the first pitch is equal to at least twice a width of one of the first metal lines, and second pitch is equal to at least twice a width of one of the second metal lines, such that, in a direction of the widths of the first metal lines, at least some of the first metal lines are insulated and spaced from at least some of the second metal lines by less than the width of one of the first metal lines.
2. The microelectronic interconnect element as claimed in claim 1 , wherein the first and second metal lines are formed by etching.
3. The microelectronic interconnect element as claimed in claim 1 , wherein at least some of the first and second metal lines are formed by plating.
4. The microelectronic interconnect element as claimed in claim 1 , wherein the widths of the first and second metal lines are less than about 60 microns.
5. The microelectronic interconnect element as claimed in claim 1 , wherein the widths of the first and second metal lines are at most about 20 microns.
6. The microelectronic interconnect element as claimed in claim 1 , wherein the widths of the first and second metal lines are uniform and are at most about 10 microns.
7. The microelectronic interconnect element as claimed in claim 1 , wherein the at least some of the first metal lines are insulated and spaced from the at least some of the second metal lines by less than 10% of the width of one of the first metal lines.
8. A microelectronic interconnect element, comprising: a plurality of first metal lines each having a lower surface whose width and length extend within a reference plane, an upper surface remote from the reference plane, and edges extending between the upper and lower surfaces, a first distance between the upper and lower surfaces of such first metal line defining a thickness of such first metal line; a plurality of second metal lines interleaved with the first metal lines in a direction of the width of the first metal lines, each of the second metal lines having an upper surface whose width and length extend within the reference plane and a lower surface remote from the reference plane, a second distance between the upper and lower surfaces of such second metal line defining a thickness of such second metal line; and a dielectric layer separating a metal line of the first metal lines from an adjacent metal line of the second metal lines, wherein each of the second metal lines have edges extending between the upper and lower surfaces of such second metal line and a spacing between the edge of one of the first metal lines and an adjacent edge of one of the second metal lines is smaller than the widths of the adjacent first and second metal lines.
9. The microelectronic interconnect element as claimed in claim 8 , wherein the first and second metal lines are formed by etching.
10. The microelectronic interconnect element as claimed in claim 8 , wherein at least some of the first and second metal lines are formed by plating.
11. The microelectronic interconnect element as claimed in claim 8 , wherein the widths of the first and second metal lines are less than about 60 microns.
12. The microelectronic interconnect element as claimed in claim 8 , wherein the widths of the first and second metal lines are at most about 20 microns.
13. The microelectronic interconnect element as claimed in claim 8 , wherein the widths of the first and second metal lines are uniform and are at most about 10 microns.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 8, 2009
June 11, 2013
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.