The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory controller, comprising: a host interface; first error detection circuitry coupled to the host interface; a memory interface; and second error detection circuitry coupled to the memory interface; wherein the first error detection circuitry is configured to: calculate error detection data for data received from the host interface; and check integrity of data transmitted to the host interface; and wherein the second error detection circuitry is configured to: calculate error correction data for data and first error correction data transmitted to the memory interface; and check integrity of data and first error correction data received from the memory interface.
A memory controller has a host interface for communicating with a host device, and a memory interface for communicating with a memory device. It includes a first error detection circuit connected to the host interface, and a second error detection circuit connected to the memory interface. The first error detection circuit calculates error detection data for data received from the host and checks the integrity of data sent to the host. The second error detection circuit calculates error correction data for data sent to memory, along with initial error detection data, and checks the integrity of data received from memory including any error correction data.
2. The memory controller of claim 1 , wherein the first error detection circuitry is configured to calculate error detection data per received sector of data.
The memory controller as described where first error detection circuitry is configured to: calculate error detection data for data received from the host interface; and check integrity of data transmitted to the host interface; and wherein the second error detection circuitry is configured to: calculate error correction data for data and first error correction data transmitted to the memory interface; and check integrity of data and first error correction data received from the memory interface, calculates error detection data for each sector of data received. This allows for granular error checking on incoming host data.
3. The memory controller of claim 2 , wherein: the data received from the host interface comprises a data payload including a number of sectors of data; and the data received from the host interface comprises streaming data.
The memory controller described where first error detection circuitry is configured to: calculate error detection data for data received from the host interface; and check integrity of data transmitted to the host interface; and wherein the second error detection circuitry is configured to: calculate error correction data for data and first error correction data transmitted to the memory interface; and check integrity of data and first error correction data received from the memory interface, that calculates error detection data for each sector of data received, handles data received from the host as a data payload consisting of multiple sectors or as streaming data providing flexibility in data handling.
4. The memory controller of claim 1 , wherein: the first error detection circuitry comprises a cyclic redundancy check (CRC) engine coupled to the host interface by a link layer and/or a transport layer; and the second error detection circuitry comprises an error correction code (ECC) engine.
The memory controller as described where first error detection circuitry is configured to: calculate error detection data for data received from the host interface; and check integrity of data transmitted to the host interface; and wherein the second error detection circuitry is configured to: calculate error correction data for data and first error correction data transmitted to the memory interface; and check integrity of data and first error correction data received from the memory interface, uses a Cyclic Redundancy Check (CRC) engine as the first error detection circuit, communicating with the host via a link or transport layer, and an Error Correction Code (ECC) engine as the second error detection circuit, implementing standard error detection/correction techniques.
5. The memory controller of claim 1 , wherein the memory controller includes: data transfer circuitry coupled to the host interface and to the first and the second error detection circuitries; and error detection memory coupled to the data transfer circuitry; wherein the error detection memory is configured to store the error detection data.
The memory controller as described where first error detection circuitry is configured to: calculate error detection data for data received from the host interface; and check integrity of data transmitted to the host interface; and wherein the second error detection circuitry is configured to: calculate error correction data for data and first error correction data transmitted to the memory interface; and check integrity of data and first error correction data received from the memory interface, includes data transfer circuitry connected to the host interface and both error detection circuits. Error detection memory is also coupled to the data transfer circuitry to store calculated error detection data facilitating error checking.
6. The memory controller of claim 5 , wherein the memory controller includes: a data buffer coupled to the data transfer circuitry and to the second error detection circuitry; wherein the data buffer is configured to buffer data for the second error detection circuitry.
The memory controller as described which includes data transfer circuitry connected to the host interface and both error detection circuits; and error detection memory coupled to the data transfer circuitry to store calculated error detection data, utilizes a data buffer connected to the data transfer circuitry and the second error detection circuit. This buffer temporarily stores data to be processed by the second error detection circuitry (ECC), allowing pipelining of data integrity operations to improve overall memory controller performance.
7. The memory controller of claim 1 , wherein the second error detection circuitry is configured to correct one or more errors in the data received from the memory interface.
The memory controller as described where first error detection circuitry is configured to: calculate error detection data for data received from the host interface; and check integrity of data transmitted to the host interface; and wherein the second error detection circuitry is configured to: calculate error correction data for data and first error correction data transmitted to the memory interface; and check integrity of data and first error correction data received from the memory interface, is capable of correcting one or more errors in the data received from the memory interface using the second error detection circuitry (ECC), enhancing data reliability.
8. The memory controller of claim 1 , wherein the memory controller is configured to transfer the data received from the host interface, the error detection data, and the error correction data across the memory interface.
The memory controller as described where first error detection circuitry is configured to: calculate error detection data for data received from the host interface; and check integrity of data transmitted to the host interface; and wherein the second error detection circuitry is configured to: calculate error correction data for data and first error correction data transmitted to the memory interface; and check integrity of data and first error correction data received from the memory interface, is configured to transfer data received from the host, the error detection data (CRC), and error correction data (ECC) across the memory interface, ensuring full data integrity during memory operations.
9. The memory controller of claim 1 , wherein the memory controller includes: data transfer circuitry coupled to the memory interface and to the first and the second error detection circuitries; wherein the data transfer circuitry is configured to receive data and corresponding error detection data from the memory interface and to transfer the data and the corresponding error detection data to the first error detection circuitry.
The memory controller as described where first error detection circuitry is configured to: calculate error detection data for data received from the host interface; and check integrity of data transmitted to the host interface; and wherein the second error detection circuitry is configured to: calculate error correction data for data and first error correction data transmitted to the memory interface; and check integrity of data and first error correction data received from the memory interface, uses data transfer circuitry coupled to the memory interface, and both the first and second error detection circuits. This allows receiving data and corresponding error detection data from the memory interface, and transferring them to the first error detection circuitry.
10. The memory controller of claim 9 , wherein the first error detection circuitry is configured to: calculate error detection data for the data received from the data transfer circuitry; and compare the calculated error detection data for the data received from the data transfer circuitry to the corresponding error detection data received from the data transfer circuitry.
The memory controller with data transfer circuitry coupled to the memory interface, and both the first and second error detection circuits for receiving data and corresponding error detection data from the memory interface, and transferring them to the first error detection circuitry, uses the first error detection circuitry to calculate error detection data for the received data from the data transfer circuitry, and then compares the calculated data with the received data to verify data integrity.
11. The memory controller of claim 9 , wherein the memory controller includes: more than one channel; channel data transfer circuitry coupled to the data transfer circuitry; a data buffer coupled to the channel data transfer circuitry and the second error detection circuitry; and error detection memory coupled to the memory interface.
The memory controller with data transfer circuitry coupled to the memory interface, and both the first and second error detection circuits for receiving data and corresponding error detection data from the memory interface, and transferring them to the first error detection circuitry, has multiple channels and channel data transfer circuitry, a data buffer connecting the channel data transfer circuitry to the second error detection circuitry, and error detection memory connecting to the memory interface allowing parallel data handling.
12. The memory controller of claim 9 , wherein the memory controller includes: more than one channel; and a channel processor and a channel memory.
The memory controller with data transfer circuitry coupled to the memory interface, and both the first and second error detection circuits for receiving data and corresponding error detection data from the memory interface, and transferring them to the first error detection circuitry, includes multiple channels, a channel processor, and channel memory allowing more complex parallel data processing.
13. The memory controller of claim 1 , wherein the memory controller includes: a host buffer coupled to the host interface; and encryption circuitry coupled to the host buffer; wherein the encryption circuitry is configured to process the data optionally for providing an encrypted output.
The memory controller as described where first error detection circuitry is configured to: calculate error detection data for data received from the host interface; and check integrity of data transmitted to the host interface; and wherein the second error detection circuitry is configured to: calculate error correction data for data and first error correction data transmitted to the memory interface; and check integrity of data and first error correction data received from the memory interface, utilizes a host buffer coupled to the host interface and encryption circuitry, to optionally encrypt data, securing data transmission between the host and the memory controller.
14. The memory controller of claim 13 , wherein the encryption circuitry comprises an advanced encryption standard (AES) engine.
The memory controller with a host buffer coupled to the host interface and encryption circuitry optionally encrypting data, uses an Advanced Encryption Standard (AES) engine as the encryption circuitry, implementing a well-known and secure encryption algorithm.
15. A memory controller, comprising: a host interface; front end error detection circuitry coupled to the host interface; a memory interface; and back end error detection circuitry coupled to the memory interface; wherein the front end error detection circuitry is configured to calculate first error detection data for corresponding data; and wherein the back end error detection circuitry is configured to: calculate second error detection data for the corresponding data; and compare the first error detection data with the second error detection data to check integrity of the corresponding data.
A memory controller uses a host interface and memory interface. It employs front-end error detection circuitry connected to the host interface, and back-end error detection circuitry connected to the memory interface. The front-end circuitry calculates first error detection data for incoming data. The back-end circuitry calculates second error detection data for the same data and compares the first and second error detection data to verify data integrity.
16. The memory controller of claim 15 , wherein the memory controller includes: data transfer circuitry coupled to the front end error detection circuitry; a back end error detection memory coupled to the data transfer circuitry and to the back end error detection circuitry; wherein the data transfer circuitry is configured to transfer the first error detection data from the front end error detection circuitry to the back end error detection memory; and wherein the back end error detection circuitry is configured to compare the first error detection data from the error detection memory with the second error detection data to check integrity of the corresponding data.
The memory controller with front-end error detection circuitry connected to the host interface, and back-end error detection circuitry connected to the memory interface, that calculates first error detection data for incoming data and compares the first and second error detection data to verify data integrity, also includes data transfer circuitry connected to the front-end detection circuitry and back-end error detection memory. The front-end data is transferred to the back-end memory for the back-end error detection circuit to use to check integrity.
17. The memory controller of claim 15 , wherein: the front end error detection circuitry comprises a cyclic redundancy check (CRC) engine; the back end error detection circuitry comprises a CRC engine; and wherein the memory controller includes an error correction code (ECC) engine coupled to the back end error detection circuitry and to the memory interface; and wherein the ECC engine is configured to calculate error correction data for the corresponding data.
The memory controller with front-end error detection circuitry connected to the host interface, and back-end error detection circuitry connected to the memory interface, that calculates first error detection data for incoming data and compares the first and second error detection data to verify data integrity, uses Cyclic Redundancy Check (CRC) engines for both front-end and back-end error detection. Additionally, it has an Error Correction Code (ECC) engine connected to the back-end circuitry and memory interface to calculate ECC data.
18. The memory controller of claim 17 , wherein the memory controller is configured to transfer the error correction data and the corresponding data across the memory interface without the first and/or the second error detection data.
The memory controller that includes Cyclic Redundancy Check (CRC) engines for both front-end and back-end error detection and an Error Correction Code (ECC) engine connected to the back-end circuitry and memory interface to calculate ECC data, transfers error correction data and associated data across the memory interface without transmitting first or second error detection data improving transfer efficiency.
19. The memory controller of claim 15 , wherein: the corresponding data comprises a direct memory access (DMA) payload; the front end error detection circuitry is configured to calculate first error detection data per sector of the DMA payload; and the back end error detection circuitry is configured to calculate second error detection data per sector of the DMA payload.
The memory controller with front-end error detection circuitry connected to the host interface, and back-end error detection circuitry connected to the memory interface, that calculates first error detection data for incoming data and compares the first and second error detection data to verify data integrity, handles Direct Memory Access (DMA) payloads where first and second error detection data is calculated per sector of the DMA payload offering granular integrity checks.
20. A memory system, comprising: one or more solid state memory devices; and a memory controller coupled to the one or more solid state memory devices, wherein the memory controller includes: front end error detection circuitry configured to calculate first error detection data for a sector of data; and back end error detection circuitry configured to: calculate second error detection data for the sector of data; and check integrity of the sector of data; and wherein the memory controller is configured to store the sector of data without the first and/or the second error detection data in the one or more solid state memory devices.
A memory system contains one or more solid-state memory devices and a connected memory controller. The controller uses front-end error detection circuitry for calculating first error detection data on a data sector, and back-end error detection circuitry calculating second error detection data to verify the sector's integrity. The system then stores the sector in memory, excluding the first and/or second error detection data to save space.
21. The system of claim 20 , wherein the back end error detection circuitry comprises a cyclic redundancy check (CRC) engine configured to compare the first error detection data with the second error detection data to check integrity of the sector of data.
The memory system with front-end error detection circuitry for calculating first error detection data on a data sector, and back-end error detection circuitry calculating second error detection data to verify the sector's integrity, where the sector is then stored in memory, excludes error detection data and uses a Cyclic Redundancy Check (CRC) engine in the back-end to compare the first and second sets of error detection data verifying integrity.
22. The system of claim 20 , wherein the system includes a physical interface coupled to a host interface of the memory controller.
The memory system with front-end error detection circuitry for calculating first error detection data on a data sector, and back-end error detection circuitry calculating second error detection data to verify the sector's integrity, where the sector is then stored in memory, excludes error detection data, also includes a physical interface connecting to the memory controller's host interface, enabling communication between the system and a host device.
23. The system of claim 22 , wherein the front end error detection circuitry comprises a cyclic redundancy check (CRC) engine coupled to the host interface by a link layer and/or a transport layer.
The memory system that includes a physical interface connecting to the memory controller's host interface with front-end error detection circuitry for calculating first error detection data on a data sector, and back-end error detection circuitry calculating second error detection data to verify the sector's integrity, where the sector is then stored in memory, excludes error detection data, uses a Cyclic Redundancy Check (CRC) engine at the front-end, connected to the host through a link or transport layer.
24. The system of claim 22 , wherein the physical interface comprises a serial interface selected from the group of serial interfaces including: universal serial bus (USB); serial advanced technology attachment (SATA); and peripheral component interconnect express (PCIe).
The memory system that includes a physical interface connecting to the memory controller's host interface with front-end error detection circuitry for calculating first error detection data on a data sector, and back-end error detection circuitry calculating second error detection data to verify the sector's integrity, where the sector is then stored in memory, excludes error detection data, offers serial interface options such as Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), or Peripheral Component Interconnect Express (PCIe).
25. The system of claim 20 , wherein the memory controller includes an error correction code (ECC) engine coupled to the back end error detection circuitry and to a memory interface, wherein the ECC engine is configured to calculate error correction data for the sector of data.
The memory system with front-end error detection circuitry for calculating first error detection data on a data sector, and back-end error detection circuitry calculating second error detection data to verify the sector's integrity, where the sector is then stored in memory, excludes error detection data, also utilizes an Error Correction Code (ECC) engine, linked to the back-end circuitry and memory interface, to calculate error correction data improving data reliability.
26. The system of claim 25 , wherein the memory controller is configured to store the sector of data and the error correction data without the error detection data in the one or more solid state memory devices when the first error detection data matches the second error detection data.
The memory system with an Error Correction Code (ECC) engine, linked to the back-end circuitry and memory interface, to calculate error correction data, includes front-end error detection circuitry for calculating first error detection data on a data sector, and back-end error detection circuitry calculating second error detection data to verify the sector's integrity, stores the sector and ECC data without storing the error detection data when the first and second checks match reducing storage overhead.
27. The system of claim 20 , wherein the front end error detection circuitry is configured to compare the first error detection data with the second error detection data to check integrity of the sector of data.
The memory system with front-end error detection circuitry for calculating first error detection data on a data sector, and back-end error detection circuitry calculating second error detection data to verify the sector's integrity, where the sector is then stored in memory, excludes error detection data and the front-end circuitry compares both the first and second sets of data to ensure integrity.
28. A method for operating a memory controller, comprising: calculating, with first error detection circuitry, error detection data for data received from a host interface coupled to the first error detection circuitry; checking integrity, with the first error detection circuitry, of data transmitted to the host interface; calculating, with second error detection circuitry, error correction data for data and first error detection data transmitted to a memory interface coupled to the second error detection circuitry; and checking integrity, with the second error detection circuitry, of data and first error correction data received from the memory interface.
A method for operating a memory controller involves calculating error detection data for data received from a host interface using a first error detection circuit, checking the integrity of data transmitted to the host using the first error detection circuit, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking the integrity of data received from the memory interface including any ECC data using the second error detection circuit.
29. The method of claim 28 , wherein calculating the error detection data for the data received from the host interface comprises calculating error detection data per sector of data received from the host interface.
The memory controller operation calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface includes calculating error detection data for each sector of data received from the host.
30. The method of claim 29 , wherein: the data received from the host interface comprises a data payload including a number of sectors of data; and the data received from the host interface comprises streaming data.
The memory controller operation calculating error detection data for each sector of data received from the host with checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, handles data either as a payload consisting of sectors, or as streaming data.
31. The method of claim 28 , wherein: the first error detection circuitry comprises a cyclic redundancy check (CRC) engine coupled to the host interface by a link layer and/or a transport layer; and the second error detection circuitry comprises an error correction code (ECC) engine.
The memory controller operation calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, implements a Cyclic Redundancy Check (CRC) engine connected by a link or transport layer to the host as the first error detection circuit and uses an Error Correction Code (ECC) engine as the second.
32. The method of claim 28 , wherein the method includes storing the error detection data in error detection memory coupled to data transfer circuitry, which is coupled to the host interface and to the first and the second error detection circuitries.
The memory controller operation calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, includes storing the error detection data in memory connected to data transfer circuitry which is in turn connected to the host and the error detection circuits.
33. The method of claim 32 , wherein the method includes buffering data for the second error detection circuitry with a data buffer coupled to the data transfer circuitry and to the second error detection circuitry.
The memory controller operation including storing the error detection data in memory connected to data transfer circuitry which is in turn connected to the host and the error detection circuits in calculating error detection data for data received from a host interface, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, also buffers data for the second detection circuit using a buffer coupled to the transfer and detection circuits.
34. The method of claim 28 , wherein the method includes correcting, with the second error detection circuitry, one or more errors in the data received from the memory interface.
The memory controller operation calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, corrects errors in the received data from the memory interface using the second detection circuit.
35. The method of claim 28 , wherein the method includes transferring the data received from the host interface, the error detection data, and the error correction data across the memory interface.
The memory controller operation calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, includes transferring all host data, detection data, and correction data across the memory interface.
36. The method of claim 28 , wherein the method includes receiving, with data transfer circuitry coupled to the memory interface and to the first and the second error detection circuitries, data and corresponding error detection data from the memory interface; and transferring, with data transfer circuitry, the data and the corresponding error detection data to the first error detection circuitry.
The memory controller operation calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, receives data from the memory interface with corresponding error detection data, using transfer circuitry connected to the memory interface and both the first and second error detection circuits, and then transfers data and corresponding detection data to the first error detection circuit.
37. The method of claim 36 , wherein calculating with the first error detection circuitry includes calculating error detection data for the data received from the data transfer circuitry; and wherein the method includes comparing, with the first error detection circuitry, the calculated error detection data for the data received from the data transfer circuitry to the corresponding error detection data received from the data transfer circuitry.
The memory controller operation that receives data from the memory interface with corresponding error detection data, using transfer circuitry connected to the memory interface and both the first and second error detection circuits, and then transfers data and corresponding detection data to the first error detection circuit calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, also involves calculating error detection data for the data received from the data transfer circuitry, and then comparing the two sets of error detection data.
38. The method of claim 36 , wherein receiving includes receiving with the data transfer circuitry coupled to more than one channel and to channel data transfer circuitry, wherein the channel data transfer circuitry is coupled to a data buffer and to the second error detection circuitry; and wherein receiving includes receiving with the data transfer circuitry coupled to the memory interface, which is coupled to error detection memory.
The memory controller operation that receives data from the memory interface with corresponding error detection data, using transfer circuitry connected to the memory interface and both the first and second error detection circuits, and then transfers data and corresponding detection data to the first error detection circuit calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, receives the data with transfer circuitry connected to multiple channels and channel data transfer circuitry. It also couples channel data transfer circuitry to a data buffer and the second detection circuit, and transfer circuitry is coupled to error detection memory.
39. The method of claim 36 , wherein receiving includes receiving with the data transfer circuitry coupled to more than one channel and to a channel processor and a channel memory.
The memory controller operation that receives data from the memory interface with corresponding error detection data, using transfer circuitry connected to the memory interface and both the first and second error detection circuits, and then transfers data and corresponding detection data to the first error detection circuit calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, uses transfer circuitry coupled to multiple channels, a channel processor, and channel memory.
40. The method of claim 28 , wherein the method includes processing, with encryption circuitry coupled to a host buffer that is coupled to the host interface, the data optionally for providing an encrypted output.
The memory controller operation calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, includes optionally encrypting the data with encryption circuitry connected to a host buffer that is connected to the host interface.
41. The method of claim 40 , wherein processing includes processing with the encryption circuitry comprising an advanced encryption standard (AES) engine.
The memory controller operation optionally encrypting the data with encryption circuitry connected to a host buffer that is connected to the host interface with calculating error detection data for data received from a host interface using a first error detection circuit, checking integrity of data transmitted to the host, calculating error correction data for data transmitted to a memory interface using a second error detection circuit and any pre-existing error detection data, and checking integrity of data received from the memory interface, uses an Advanced Encryption Standard (AES) engine as the encryption circuitry.
42. A method for operating a memory controller, comprising: calculating, with front end error detection circuitry coupled to a host interface, first error detection data for corresponding data; calculating, with back end error detection circuitry coupled to a memory interface, second error detection data for the corresponding data; and comparing, with the back end error detection circuitry, the first error detection data with the second error detection data to check integrity of the corresponding data.
A method for operating a memory controller calculates first error detection data for corresponding data using front-end error detection circuitry connected to a host interface, calculates second error detection data for the same data using back-end error detection circuitry connected to a memory interface, and compares the two sets of data using the back-end circuitry to verify data integrity.
43. The method of claim 42 , wherein the method includes: transferring the first error detection data from the front end error detection circuitry to a back end error detection memory via data transfer circuitry coupled to the front end error detection circuitry and to the back end error detection memory; and comparing, with the back end error detection circuitry, the first error detection data from the error detection memory with the second error detection data to check integrity of the corresponding data.
The memory controller operation calculating first error detection data for corresponding data using front-end error detection circuitry connected to a host interface, calculating second error detection data for the same data using back-end error detection circuitry connected to a memory interface, and comparing the two sets of data using the back-end circuitry to verify data integrity, includes transferring the first error data from the front-end circuitry to back-end memory using data transfer circuitry, and then comparing the two sets of data using the back-end circuitry.
44. The method of claim 42 , wherein: the front end error detection circuitry comprises a cyclic redundancy check (CRC) engine; the back end error detection circuitry comprises a CRC engine; and the method includes calculating, with an error correction code (ECC) engine coupled to the back end error detection circuitry and to the memory interface, error correction data from the corresponding data.
The memory controller operation calculating first error detection data for corresponding data using front-end error detection circuitry connected to a host interface, calculating second error detection data for the same data using back-end error detection circuitry connected to a memory interface, and comparing the two sets of data using the back-end circuitry to verify data integrity, utilizes Cyclic Redundancy Check (CRC) engines for both front and back-end circuitry, and calculates error correction data using ECC coupled to the back-end and the memory interface.
45. The method of claim 44 , wherein the method includes transferring the error correction data and the corresponding data across the memory interface without the first and/or the second error detection data.
The memory controller operation calculating first error detection data for corresponding data using front-end error detection circuitry connected to a host interface, calculating second error detection data for the same data using back-end error detection circuitry connected to a memory interface, and comparing the two sets of data using the back-end circuitry to verify data integrity with Cyclic Redundancy Check (CRC) engines for both front and back-end circuitry, and calculating error correction data using ECC coupled to the back-end and the memory interface, transfers ECC data and corresponding data across the memory interface without transferring the detection data.
46. The method of claim 42 , wherein: the corresponding data comprises a direct memory access (DMA) payload; calculating, with the front end error detection circuitry, comprises calculating first error detection data per sector of the DMA payload; and calculating, with the back end error detection circuitry, comprises calculating second error detection data per sector of the DMA payload.
The memory controller operation calculating first error detection data for corresponding data using front-end error detection circuitry connected to a host interface, calculating second error detection data for the same data using back-end error detection circuitry connected to a memory interface, and comparing the two sets of data using the back-end circuitry to verify data integrity, handles Direct Memory Access (DMA) payloads and calculates the first and second data on a per-sector basis.
47. A method for operating a memory system, comprising: calculating, with front end error detection circuitry in a memory controller coupled to one or more solid state memory devices, first error detection data for a sector of data; calculating, with back end error detection circuitry in the memory controller, second error detection data for the sector of data; checking integrity, with back end error detection circuitry, of the sector of data; storing the sector of data without the first and/or the second error detection data in the one or more solid state memory devices.
A method for operating a memory system with a memory controller connected to solid-state memory devices involves calculating first error detection data for a data sector using front-end circuitry in the controller, calculating second error detection data for the sector using back-end circuitry, verifying the sector's integrity using the back-end circuitry, and storing the data sector in memory without storing either set of error detection data.
48. The method of claim 47 , wherein the method includes comparing, with the back end error detection circuitry comprising a cyclic redundancy check (CRC) engine, the first error detection data with the second error detection data to check integrity of the sector of data.
The memory system operation calculating first error detection data for a data sector using front-end circuitry in the controller, calculating second error detection data for the sector using back-end circuitry, verifying the sector's integrity using the back-end circuitry, and storing the data sector in memory without storing either set of error detection data, uses a CRC in the back-end circuitry to compare both sets of error data and ensure integrity.
49. The method of claim 47 , wherein operating the memory system includes operating a physical interface coupled to a host interface of the memory controller.
The memory system operation calculating first error detection data for a data sector using front-end circuitry in the controller, calculating second error detection data for the sector using back-end circuitry, verifying the sector's integrity using the back-end circuitry, and storing the data sector in memory without storing either set of error detection data, also involves operating a physical interface connected to the host interface of the memory controller.
50. The method of claim 49 , wherein the front end error detection circuitry comprises a cyclic redundancy check (CRC) engine coupled to the host interface by a link layer and/or a transport layer.
The memory system operation including operating a physical interface connected to the host interface of the memory controller with calculating first error detection data for a data sector using front-end circuitry in the controller, calculating second error detection data for the sector using back-end circuitry, verifying the sector's integrity using the back-end circuitry, and storing the data sector in memory without storing either set of error detection data, utilizes a CRC in the front-end circuitry and is connected via a link or transport layer.
51. The method of claim 49 , wherein the physical interface comprises a serial interface selected from the group of serial interfaces including: universal serial bus (USB); serial advanced technology attachment (SATA); and peripheral component interconnect express (PCIe).
The memory system operation including operating a physical interface connected to the host interface of the memory controller with calculating first error detection data for a data sector using front-end circuitry in the controller, calculating second error detection data for the sector using back-end circuitry, verifying the sector's integrity using the back-end circuitry, and storing the data sector in memory without storing either set of error detection data, and utilizes a serial interface for the physical layer such as USB, SATA, or PCIe.
52. The method of claim 47 , wherein the method includes calculating, with an error correction code (ECC) engine coupled to the back end error detection circuitry and to a memory interface, error correction data for the sector of data.
The memory system operation calculating first error detection data for a data sector using front-end circuitry in the controller, calculating second error detection data for the sector using back-end circuitry, verifying the sector's integrity using the back-end circuitry, and storing the data sector in memory without storing either set of error detection data, also calculates error correction data with an ECC connected to both the back-end and the memory interface.
53. The method of claim 52 , wherein storing comprises storing the sector of data and the error correction data without the error detection data in the one or more solid state memory devices when the first error detection data matches the second error detection data.
The memory system operation that also calculates error correction data with an ECC connected to both the back-end and the memory interface with calculating first error detection data for a data sector using front-end circuitry in the controller, calculating second error detection data for the sector using back-end circuitry, verifying the sector's integrity using the back-end circuitry, and storing the data sector in memory without storing either set of error detection data, stores the data sector and ECC data in memory but not the error detection data, if the two data sets match.
54. The method of claim 47 , wherein the method includes comparing, with the front end error detection circuitry, the first error detection data with the second error detection data to check integrity of the sector of data.
The memory system operation calculating first error detection data for a data sector using front-end circuitry in the controller, calculating second error detection data for the sector using back-end circuitry, verifying the sector's integrity using the back-end circuitry, and storing the data sector in memory without storing either set of error detection data, compares both sets of error data in the front-end circuitry.
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February 18, 2009
June 18, 2013
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