Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a capacitor, comprising: forming a tungsten nitride, bottom electrode layer; forming a tungsten oxide buffer layer overlying the bottom electrode layer; annealing the buffer layer to form an orthorhombic structure; forming a dielectric layer overlying the tungsten oxide buffer layer; and forming a top electrode layer overlying the dielectric layer.
2. The method of claim 1 , further comprising patterning the top electrode layer, the buffer layer, the dielectric layer, and the bottom electrode layer to define the capacitor.
3. The method of claim 1 , wherein the method is performed in the order presented.
4. The method of claim 1 , wherein forming the bottom electrode includes forming WN n ; 2<n<=6.
5. A method of forming a capacitor, comprising: forming an insulating layer on a substrate; forming an opening in the insulating layer, wherein the opening has a bottom portion overlying an exposed portion of the substrate and sidewall portions defined by the insulating layer; forming a bottom electrode layer, which includes tungsten nitride, overlying the insulating layer, the exposed portion of the substrate and the sidewall portions; forming an orthorhombic tungsten oxide buffer layer overlying the bottom electrode layer; forming a dielectric layer overlying the tungsten oxide buffer layer; forming a top electrode layer overlying the dielectric layer; and patterning the top electrode layer, dielectric layer, tungsten oxide buffer layer and bottom electrode layer to thereby define the capacitor.
6. The method of claim 5 , wherein forming the tungsten oxide buffer layer comprises oxidizing the bottom electrode layer to form the buffer layer, and annealing the buffer layer.
7. The method of claim 6 , wherein the buffer layer is annealed at a temperature of over 650 degrees Celsius.
8. The method of claim 5 , wherein the buffer layer is annealed at a temperature of at least 700 degrees Celsius.
9. The method of claim 5 , wherein forming the bottom electrode includes forming WN n ; 2<n<=6.
10. A method of forming a capacitor, comprising: forming an insulating layer on a substrate; forming an opening in the insulating layer, wherein the opening has a bottom portion overlying an exposed portion of the substrate and sidewall portions defined by the insulating layer; forming a tungsten nitride bottom electrode layer overlying the insulating layer, the exposed portion of the substrate and the sidewall portions; forming a tungsten oxide buffer layer overlying the bottom electrode layer, wherein the buffer layer has an orthorhombic crystal structure; forming a dielectric layer overlying the buffer layer; forming a top electrode layer overlying the dielectric layer; and patterning the top electrode layer, dielectric layer, buffer layer and bottom electrode layer to thereby define the capacitor.
11. The method of claim 10 , wherein forming the bottom electrode includes forming WN 2 .
12. A method of forming a capacitor, comprising: forming an insulating layer on a substrate; forming an opening in the insulating layer, wherein the opening has a bottom portion overlying an exposed portion of the substrate and sidewall portions defined by the insulating layer; forming a tungsten nitride bottom electrode layer overlying the insulating layer, the exposed portion of the substrate and the sidewall portions; oxidizing the bottom electrode layer to form a tungsten oxide buffer layer overlying the bottom electrode layer; annealing the buffer layer to an orthorhombic crystal lattice; forming a dielectric layer overlying the buffer layer; forming a top electrode layer overlying the dielectric layer; and patterning the top electrode layer, dielectric layer, buffer layer and bottom electrode layer to thereby define the capacitor.
13. The method according to claim 12 , wherein annealing the buffer layer includes annealing at a temperature of at least 700 degrees Celsius.
14. The method of claim 12 , wherein forming the bottom electrode includes forming WN 2 .
15. A method of forming a capacitor, comprising: forming an insulating layer on a substrate; forming an opening in the insulating layer, wherein the opening has a bottom portion overlying an exposed portion of the substrate and sidewall portions defined by the insulating layer; depositing a tungsten nitride bottom electrode layer overlying the insulating layer, the exposed portion of the substrate and the sidewall portions; oxidizing the bottom electrode layer to form a tungsten trioxide buffer layer overlying the bottom electrode layer; annealing the buffer layer at a temperature of at least 700 degrees Celsius to have an orthorhombic crystal lattice; depositing a tantalum oxide dielectric layer overlying the buffer layer; depositing a metal top electrode layer overlying the dielectric layer; and patterning the top electrode layer, dielectric layer, buffer layer and bottom electrode layer to thereby define the capacitor.
16. The method of claim 15 , wherein the metal top electrode includes a noble metal.
17. The method of claim 15 , wherein the top electrode includes a platinum alloy.
18. A method of forming a capacitor, comprising: forming a first electrode layer, wherein the first electrode layer comprises a metal nitride having a metal component; forming a buffer layer having an orthorhombic crystal structure overlying the first electrode layer, wherein the buffer layer comprises a metal oxide having a composition of the form MO x , wherein M is a metal component selected from the group consisting of chromium, cobalt, hafnium, iridium, molybdenum, niobium, osmium, rhenium, rhodium, ruthenium, tantalum, titanium, tungsten, vanadium and zirconium; forming a dielectric layer overlying the buffer layer; forming a second electrode layer overlying the buffer layer, wherein the second electrode layer comprises a metal nitride having a metal component; and patterning the second electrode layer, dielectric layer, buffer layer and first electrode layer to thereby define the capacitor.
19. The method of claim 18 , wherein the metal component of the first electrode layer is tungsten.
20. The method of claim 18 , wherein the metal component M of the buffer layer is selected to be the same as the metal component of the first electrode layer.
21. The method of claim 18 , wherein the dielectric layer comprises a metal oxide dielectric material.
22. The method of claim 18 , wherein the method is performed in the order presented.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 31, 2007
June 25, 2013
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