An insulating material interposed between two conductive materials can experience plasma process induced damage (PPID) when a plasma process is used to deposit a dielectric onto one of the conductive materials. This PPID can be reduced by reducing electric charge accumulation on the one conductive material during the plasma process dielectric deposition.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electrical circuit apparatus comprising: a gate oxide on a substrate; a gate electrode on the gate oxide; a silicon nitride or silicon oxynitride etch stop layer over the gate electrode, wherein the etch stop layer has a refractive index of at least 2.15; a fluorine doped high-density plasma oxide over the etch stop layer; wherein the etch stop layer has an extinction coefficient value in a range from approximately 1.50 to approximately 1.65; a dielectric layer between the etch stop layer and a metal layer electrically connected to the gate electrode; and an oxide liner between the metal layer and the fluorine doped high-density plasma oxide.
2. The apparatus of claim 1 , further comprising: an opening through the dielectric layer and the etch stop layer over the gate electrode.
3. The apparatus of claim 2 , further comprising: a metal region within the opening between the gate electrode and the metal layer.
4. The apparatus of claim 2 , wherein the dielectric layer is phosphorus-doped tetraethyl orthosilicate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 5, 2004
June 25, 2013
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