An insulating material interposed between two conductive materials can experience plasma process induced damage (PPID) when a plasma process is used to deposit a dielectric onto one of the conductive materials. This PPID can be reduced by reducing electric charge accumulation on the one conductive material during the plasma process dielectric deposition.
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1. An electrical circuit apparatus comprising: a gate oxide on a substrate; a gate electrode on the gate oxide; a silicon nitride or silicon oxynitride etch stop layer over the gate electrode, wherein the etch stop layer has a refractive index of at least 2.15; a fluorine doped high-density plasma oxide over the etch stop layer; wherein the etch stop layer has an extinction coefficient value in a range from approximately 1.50 to approximately 1.65; a dielectric layer between the etch stop layer and a metal layer electrically connected to the gate electrode; and an oxide liner between the metal layer and the fluorine doped high-density plasma oxide.
An integrated circuit is built to reduce damage from plasma processing. It includes a gate oxide layer on a substrate, and a gate electrode on top of that. A silicon nitride or silicon oxynitride etch stop layer with a high refractive index (at least 2.15) and a specific extinction coefficient (1.50-1.65) sits above the gate electrode. A fluorine-doped high-density plasma oxide layer is placed over the etch stop layer. A dielectric layer insulates the etch stop layer from a metal layer connected to the gate electrode. Finally, an oxide liner sits between the metal layer and the fluorine-doped high-density plasma oxide. This structure aims to minimize charge buildup during plasma processes, thus preventing damage.
2. The apparatus of claim 1 , further comprising: an opening through the dielectric layer and the etch stop layer over the gate electrode.
The integrated circuit described previously also contains an opening through the dielectric layer and the etch stop layer directly above the gate electrode. This opening provides a pathway or connection point for other circuit elements. The structure consists of a gate oxide on a substrate; a gate electrode on the gate oxide; a silicon nitride or silicon oxynitride etch stop layer over the gate electrode, wherein the etch stop layer has a refractive index of at least 2.15; a fluorine doped high-density plasma oxide over the etch stop layer; wherein the etch stop layer has an extinction coefficient value in a range from approximately 1.50 to approximately 1.65; a dielectric layer between the etch stop layer and a metal layer electrically connected to the gate electrode; and an oxide liner between the metal layer and the fluorine doped high-density plasma oxide.
3. The apparatus of claim 2 , further comprising: a metal region within the opening between the gate electrode and the metal layer.
The integrated circuit described previously, which also has an opening through the dielectric and etch stop layers over the gate electrode, also includes a metal region within that opening. This metal region sits between the gate electrode and the metal layer above the dielectric. The structure includes a gate oxide on a substrate; a gate electrode on the gate oxide; a silicon nitride or silicon oxynitride etch stop layer over the gate electrode, wherein the etch stop layer has a refractive index of at least 2.15; a fluorine doped high-density plasma oxide over the etch stop layer; wherein the etch stop layer has an extinction coefficient value in a range from approximately 1.50 to approximately 1.65; a dielectric layer between the etch stop layer and a metal layer electrically connected to the gate electrode; and an oxide liner between the metal layer and the fluorine doped high-density plasma oxide.
4. The apparatus of claim 2 , wherein the dielectric layer is phosphorus-doped tetraethyl orthosilicate.
The integrated circuit described previously, which also has an opening through the dielectric layer and the etch stop layer directly above the gate electrode, uses phosphorus-doped tetraethyl orthosilicate (P-TEOS) as the material for the dielectric layer. The structure consists of a gate oxide on a substrate; a gate electrode on the gate oxide; a silicon nitride or silicon oxynitride etch stop layer over the gate electrode, wherein the etch stop layer has a refractive index of at least 2.15; a fluorine doped high-density plasma oxide over the etch stop layer; wherein the etch stop layer has an extinction coefficient value in a range from approximately 1.50 to approximately 1.65; a dielectric layer between the etch stop layer and a metal layer electrically connected to the gate electrode; and an oxide liner between the metal layer and the fluorine doped high-density plasma oxide.
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August 5, 2004
June 25, 2013
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