Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for handling interrupts of multiple instruction threads within a multi-thread processing environment, the method comprising: interleavingly fetching and issuing instructions of a plurality of instruction execution threads for execution by an execution block of the multi-thread processing environment, wherein the plurality of instruction execution threads comprises (i) a subset of the plurality of instruction execution threads and (ii) a first instruction execution thread that is not included in the subset of the plurality of instruction execution threads; for each of the plurality of instruction execution threads, providing a corresponding interrupt signal via a corresponding interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the corresponding instruction execution thread, such that a plurality of interrupt signals via a corresponding plurality of interrupt signal lines are provided for the corresponding plurality of instruction execution threads; masking the subset of the plurality of instruction execution threads, such that each of the subset of the plurality of instruction threads ignores the corresponding interrupt signal; and in response to masking the subset of the plurality of instruction execution threads, processing, by the first instruction execution thread, one or more interrupt signals corresponding to one or more instruction execution threads of the subset of the plurality of instruction execution threads, wherein the plurality of interrupt signal lines are physically separate and distinct signal lines.
In a multi-threaded processor, multiple instruction threads are interleaved and executed by an execution block. Each thread has a dedicated interrupt signal line. A subset of threads can be masked to ignore their interrupts. When a subset of threads is masked, a remaining thread (not in the subset) will process the interrupt signals from the masked threads. All interrupt signal lines are physically separate. This allows one thread to handle interrupts for other threads when those other threads are temporarily unable to respond to interrupts.
2. The method of claim 1 , wherein the plurality of interrupt signal lines are directly electrically coupled to one another.
In the multi-threaded processor interrupt handling system where multiple instruction threads are interleaved and executed, with each thread having a dedicated and physically separate interrupt signal line, and a subset of threads can be masked to ignore their interrupts, a remaining thread (not in the subset) will process the interrupt signals from the masked threads. The dedicated interrupt signal lines for each thread are directly electrically connected to each other.
3. The method of claim 1 , further comprising: while processing the one or more of the interrupt signals, disabling fetching and issuing of instructions of each of the plurality of instruction execution threads.
In the multi-threaded processor interrupt handling system where multiple instruction threads are interleaved and executed, with each thread having a dedicated interrupt signal line, and a subset of threads can be masked to ignore their interrupts, a remaining thread (not in the subset) will process the interrupt signals from the masked threads. While this remaining thread is actively processing these interrupts, instruction fetching and issuing for *all* threads is temporarily disabled.
4. The method of claim 1 , wherein processing the one or more of the interrupt signals further comprises: processing the one or more of the interrupt signals either (i) during masking the subset of the plurality of instruction execution threads or (ii) subsequent to an end of masking the subset of the plurality of instruction execution threads.
In the multi-threaded processor interrupt handling system where multiple instruction threads are interleaved and executed, with each thread having a dedicated interrupt signal line, and a subset of threads can be masked to ignore their interrupts, a remaining thread (not in the subset) will process the interrupt signals from the masked threads. The interrupt processing by the remaining thread can occur either while the subset of threads is *actively* masked, or *after* the masking of the subset has ended.
5. The method of claim 1 , wherein processing the one or more of the interrupt signals further comprises: processing the one or more of the interrupt signals by fetching and issuing instructions of at least one interrupt service routine.
In the multi-threaded processor interrupt handling system where multiple instruction threads are interleaved and executed, with each thread having a dedicated interrupt signal line, and a subset of threads can be masked to ignore their interrupts, a remaining thread (not in the subset) will process the interrupt signals from the masked threads. The interrupt processing is done by fetching and issuing instructions from an interrupt service routine (ISR).
6. The method of claim 5 , wherein the at least one interrupt service routine is a shared interrupt service routine that services the plurality of interrupt signals.
In the multi-threaded processor interrupt handling system where multiple instruction threads are interleaved and executed, with each thread having a dedicated interrupt signal line, and a subset of threads can be masked to ignore their interrupts, a remaining thread (not in the subset) will process the interrupt signals from the masked threads and uses an interrupt service routine (ISR) to do so. The ISR used is a *shared* ISR, meaning it handles interrupt signals from multiple threads.
7. The method of claim 1 , wherein processing the one or more of the interrupt signals further comprises: while fetching and issuing of instructions of the first instruction execution thread, processing the one or more of the interrupt signals.
In the multi-threaded processor interrupt handling system where multiple instruction threads are interleaved and executed, with each thread having a dedicated interrupt signal line, and a subset of threads can be masked to ignore their interrupts, a remaining thread (not in the subset) will process the interrupt signals from the masked threads. While the remaining thread is fetching and issuing its *own* instructions, it *also* processes the interrupt signals from the masked threads.
8. The method of claim 1 , wherein processing the one or more of the interrupt signals further comprises: while fetching and issuing of instructions of the first instruction execution thread, receiving the one or more of the interrupt signals; while fetching and issuing of instructions of the first instruction execution thread, queuing the received one or more of the interrupt signals; and subsequent to completing the fetching and issuing of instructions of the first instruction execution thread, processing the queued one or more of the interrupt signals.
In the multi-threaded processor interrupt handling system where multiple instruction threads are interleaved and executed, with each thread having a dedicated interrupt signal line, and a subset of threads can be masked to ignore their interrupts, a remaining thread (not in the subset) will process the interrupt signals from the masked threads. While the remaining thread is fetching and issuing its *own* instructions, it *receives* and *queues* the interrupt signals from the masked threads. After it finishes its current instruction processing, it then processes the queued interrupt signals.
9. An article of manufacture comprising a non-transitory storage medium having instructions stored thereon that, when executed, cause a multi-thread processing environment to: interleavingly fetch and issue instructions of a plurality of instruction execution threads for execution by an execution block of the multi-thread processing environment, wherein the plurality of instruction execution threads comprises (i) a subset of the plurality of instruction execution threads and (ii) a first instruction execution thread that is not included in the subset of the plurality of instruction execution threads; for each of the plurality of instruction execution threads, provide a corresponding interrupt signal via a corresponding interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the corresponding instruction execution thread, such that a plurality of interrupt signals via a corresponding plurality of interrupt signal lines are provided for the corresponding plurality of instruction execution threads; mask the subset of the plurality of instruction execution threads, such that each of the subset of the plurality of instruction threads ignores the corresponding interrupt signal; and in response to masking the subset of the plurality of instruction execution threads, process, by the first instruction execution thread, one or more interrupt signals corresponding to one or more instruction execution threads of the subset of the plurality of instruction execution threads, wherein the plurality of interrupt signal lines are physically separate and distinct signal lines.
Software instructions on a storage medium enable a multi-threaded processor to: interleave and execute multiple instruction threads; provide each thread with a dedicated, physically separate interrupt signal line; allow a subset of threads to be masked to ignore interrupts; and have a remaining thread (not in the subset) process the interrupt signals from the masked threads. This allows flexible interrupt handling where one thread takes over interrupt processing for others when needed.
10. The article of manufacture of claim 9 , wherein: the plurality of interrupt signal lines are directly electrically coupled to one another.
Software instructions on a storage medium enable a multi-threaded processor to: interleave and execute multiple instruction threads; provide each thread with a dedicated, physically separate interrupt signal line; allow a subset of threads to be masked to ignore interrupts; and have a remaining thread (not in the subset) process the interrupt signals from the masked threads, AND wherein the dedicated interrupt signal lines for each thread are directly electrically connected to each other.
11. The article of manufacture of claim 9 , wherein the instructions, when executed, further cause the multi-thread processing environment to: while processing the one or more of the interrupt signals, disable fetching and issuing of instructions of each of the plurality of instruction execution threads.
Software instructions on a storage medium enable a multi-threaded processor to: interleave and execute multiple instruction threads; provide each thread with a dedicated, physically separate interrupt signal line; allow a subset of threads to be masked to ignore interrupts; have a remaining thread (not in the subset) process the interrupt signals from the masked threads, AND while the remaining thread is actively processing these interrupts, instruction fetching and issuing for *all* threads is temporarily disabled.
12. The article of manufacture of claim 9 , wherein the instructions, when executed, further cause the multi-thread processing environment to process the one or more of the interrupt signals by: processing the one or more of the interrupt signals either (i) during masking the subset of the plurality of instruction execution threads or (ii) subsequent to an end of masking the subset of the plurality of instruction execution threads.
Software instructions on a storage medium enable a multi-threaded processor to: interleave and execute multiple instruction threads; provide each thread with a dedicated, physically separate interrupt signal line; allow a subset of threads to be masked to ignore interrupts; have a remaining thread (not in the subset) process the interrupt signals from the masked threads, AND the interrupt processing by the remaining thread can occur either while the subset of threads is *actively* masked, or *after* the masking of the subset has ended.
13. The article of manufacture of claim 9 , wherein the instructions, when executed, further cause the multi-thread processing environment to process the one or more of the interrupt signals by: fetching and issuing instructions of at least one interrupt service routine.
Software instructions on a storage medium enable a multi-threaded processor to: interleave and execute multiple instruction threads; provide each thread with a dedicated, physically separate interrupt signal line; allow a subset of threads to be masked to ignore interrupts; have a remaining thread (not in the subset) process the interrupt signals from the masked threads, AND the interrupt processing is done by fetching and issuing instructions from an interrupt service routine (ISR).
14. The article of manufacture of claim 13 , wherein the at least one interrupt service routine is a shared interrupt service routine that services the plurality of interrupt signals.
Software instructions on a storage medium enable a multi-threaded processor to: interleave and execute multiple instruction threads; provide each thread with a dedicated, physically separate interrupt signal line; allow a subset of threads to be masked to ignore interrupts; have a remaining thread (not in the subset) process the interrupt signals from the masked threads, AND wherein the remaining thread uses a *shared* ISR, meaning it handles interrupt signals from multiple threads.
15. The article of manufacture of claim 9 , wherein the instructions, when executed, further cause the multi-thread processing environment to process the one or more of the interrupt signals by: while fetching and issuing of instructions of the first instruction execution thread, processing the one or more of the interrupt signals.
Software instructions on a storage medium enable a multi-threaded processor to: interleave and execute multiple instruction threads; provide each thread with a dedicated, physically separate interrupt signal line; allow a subset of threads to be masked to ignore interrupts; have a remaining thread (not in the subset) process the interrupt signals from the masked threads, AND while the remaining thread is fetching and issuing its *own* instructions, it *also* processes the interrupt signals from the masked threads.
16. The article of manufacture of claim 9 , wherein the instructions, when executed, further cause the multi-thread processing environment to process the one or more of the interrupt signals by: while fetching and issuing of instructions of the first instruction execution thread, receiving the one or more of the interrupt signals; while fetching and issuing of instructions of the first instruction execution thread, queuing the received one or more of the interrupt signals; and subsequent to completing the fetching and issuing of instructions of the first instruction execution thread, processing the queued one or more of the interrupt signals.
Software instructions on a storage medium enable a multi-threaded processor to: interleave and execute multiple instruction threads; provide each thread with a dedicated, physically separate interrupt signal line; allow a subset of threads to be masked to ignore interrupts; have a remaining thread (not in the subset) process the interrupt signals from the masked threads, AND while the remaining thread is fetching and issuing its *own* instructions, it *receives* and *queues* the interrupt signals from the masked threads, and after it finishes its current instruction processing, it then processes the queued interrupt signals.
17. A method for handling interrupts of multiple instruction threads within a multi-thread processing environment, the method comprising: interleavingly fetching and issuing instructions of a plurality of instruction execution threads for execution by an execution block of the multi-thread processing environment, wherein the plurality of instruction execution threads comprises (i) a subset of the plurality of instruction execution threads and (ii) a first instruction execution thread that is not included in the subset of the plurality of instruction execution threads; for each of the plurality of instruction execution threads, providing a corresponding interrupt signal via a corresponding interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the corresponding instruction execution thread, such that a plurality of interrupt signals via a corresponding plurality of interrupt signal lines are provided for the corresponding plurality of instruction execution threads; masking the subset of the plurality of instruction execution threads, such that each of the subset of the plurality of instruction threads ignores the corresponding interrupt signal; and in response to masking the subset of the plurality of instruction execution threads, processing, by the first instruction execution thread, one or more interrupt signals corresponding to one or more instruction execution threads of the subset of the plurality of instruction execution threads, wherein the plurality of interrupt signal lines are directly electrically coupled to one another.
18. An article of manufacture comprising a non-transitory storage medium having instructions stored thereon that, when executed, cause a multi-thread processing environment to: interleavingly fetch and issue instructions of a plurality of instruction execution threads for execution by an execution block of the multi-thread processing environment, wherein the plurality of instruction execution threads comprises (i) a subset of the plurality of instruction execution threads and (ii) a first instruction execution thread that is not included in the subset of the plurality of instruction execution threads; for each of the plurality of instruction execution threads, provide a corresponding interrupt signal via a corresponding interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the corresponding instruction execution thread, such that a plurality of interrupt signals via a corresponding plurality of interrupt signal lines are provided for the corresponding plurality of instruction execution threads; mask the subset of the plurality of instruction execution threads, such that each of the subset of the plurality of instruction threads ignores the corresponding interrupt signal; and in response to masking the subset of the plurality of instruction execution threads, process, by the first instruction execution thread, one or more interrupt signals corresponding to one or more instruction execution threads of the subset of the plurality of instruction execution threads, wherein the plurality of interrupt signal lines are directly electrically coupled to one another.
Software instructions on a storage medium enable a multi-threaded processor to: interleave and execute multiple instruction threads; provide each thread with a dedicated, physically separate interrupt signal line; allow a subset of threads to be masked to ignore interrupts; and have a remaining thread (not in the subset) process the interrupt signals from the masked threads. All interrupt signal lines are directly electrically connected to each other. This allows flexible interrupt handling where one thread takes over interrupt processing for others when needed.
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May 24, 2012
June 25, 2013
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