Described herein are systems and methods for stress avoidance and stress compensation in low power Liquid Crystal Displays (LCDs). In an exemplary embodiment, two or more transistors in series are used to hold charge on an LCD pixel. To avoid negative stress on the transistors, the transistors are alternately driven to an “off” state so that no one transistor sees a long “off” time. In another embodiment, stress on transistors of a display circuit are measured and controlled negative stress is applied to the transistors to compensate for the measured stress.
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1. A method of operating a display circuit, wherein the display circuit comprises a plurality of pixel circuits, each pixel circuit comprising at least two transistors in series connected to a pixel of a Liquid Crystal Display (LCD), the method comprising: performing frame loading operations, wherein each frame loading operation updates a display image of the LCD; and between frame loading operations, for each pixel circuit, holding a charge of the corresponding LCD pixel, wherein to hold a charge of a LCD pixel of a pixel circuit between frame loading operations a negative gate bias voltage is alternately applied to the transistors of said transistors in series of the pixel circuit, and when the negative gate bias voltage is applied to a least one transistor of said transistors in series of the pixel circuit, a positive gate bias voltage is applied to the at least one other transistor of said transistors in series of the pixel circuit, thereby applying a positive stress to compensate for negative stress accumulated on said at least one other transistor of said transistors in series when the negative gate bias is applied, wherein said negative gate bias voltage and positive gate bias voltage are alternately applied between frame loading operations to each one of said transistors in series.
A method for operating an active matrix LCD display to reduce transistor stress involves using pixel circuits with at least two transistors connected in series for each pixel. During normal operation between frame updates, instead of applying a constant voltage, the method alternates the gate bias voltage applied to each transistor. When one transistor has a negative gate bias voltage, the other transistor in series receives a positive gate bias voltage. This applies positive stress to the second transistor which compensates for negative stress previously accumulated when the negative voltage was applied to it. The negative and positive bias voltages are repeatedly alternated between the transistors in series to balance stress and improve transistor lifespan.
2. The method of claim 1 , further comprising alternately applying the negative gate bias voltage and the positive gate bias voltage to one of the transistors of said transistors in series of the pixel circuit at a rate of 60 Hz or greater.
In the active matrix LCD display described previously, where each pixel circuit uses at least two transistors in series, the method further specifies that the alternating negative and positive gate bias voltage applied to each of the transistors in series should occur at a rate of 60 Hz or greater. This means that each transistor's gate bias switches between negative and positive voltage at least 60 times per second.
3. The method of claim 1 , wherein performing a frame loading operation comprises, for each pixel circuit: applying a positive gate bias voltage to each transistor of said transistors in series of the pixel circuit to form a conduction path through the transistors to the corresponding LCD pixel; and sending a charge through the conduction path to the LCD pixel to charge the corresponding LCD pixel.
In the active matrix LCD display operation described previously, the process of updating the image on the LCD (frame loading) involves applying a positive gate bias voltage to all of the transistors in series in a pixel circuit. This effectively creates a conductive path through the transistors to the corresponding LCD pixel. Charge is then sent through this conduction path to charge the LCD pixel, thus setting its desired brightness or color for that frame.
4. The method of claim 1 , wherein the display circuit comprises a plurality of row and column select transistors connected to the pixel circuits, the method further comprising performing frame loading operation, wherein each frame loading operation updates a display age of the LCD and comprises applying gate bias voltages to the row and column select transistors; and between frame loading operations, applying a negative gate bias to the row and column select transistors, thereby applying negative stress to compensate for positive stress accumulated on said row and column select transistors during the frame loading operations.
In the active matrix LCD display operation where each pixel circuit includes at least two transistors connected to the LCD pixel, the display circuit further includes row and column select transistors to control pixel addressing. During frame loading (updating the display image), gate bias voltages are applied to the row and column select transistors. Between frame loading operations, a negative gate bias is applied to these row and column select transistors. This negative gate bias applies negative stress to compensate for the positive stress that accumulates on these transistors during the frame loading operations, extending their lifespan.
5. The method of claim 4 , further comprising: periodically measuring threshold voltage shifts in the row and column select transistors; and adjusting the amount of negative stress applied to the row and column select transistors based on the measured threshold voltage shifts.
In the active matrix LCD display operation described previously, involving row and column select transistors and negative gate bias to compensate positive stress, the method further includes periodically measuring the threshold voltage shifts in the row and column select transistors. Based on these measurements, the amount of negative stress applied to the row and column select transistors is adjusted to ensure optimal compensation and prevent excessive stress in either direction.
6. The method of claim 5 , wherein adjusting the amount of negative stress comprises adjusting an amount of time that a negative voltage is applied to the row and column select transistors.
In the active matrix LCD display operation described previously, where the negative stress applied to the row and column select transistors is adjusted based on measured threshold voltage shifts, the adjustment is performed by changing the duration of time that the negative voltage is applied to the row and column select transistors. This provides a direct control over the amount of negative stress applied.
7. The method of claim 5 , wherein adjusting the amount of negative stress comprises adjusting a waveform of a negative voltage applied to the row and column select transistors.
In the active matrix LCD display operation described previously, where the negative stress applied to the row and column select transistors is adjusted based on measured threshold voltage shifts, the adjustment is performed by modifying the waveform of the negative voltage applied to the row and column select transistors. This allows for more fine-grained control over the negative stress application compared to simply changing the duration.
8. A display circuit for a pixel array, comprising: a row and column driver; and a plurality of pixel circuits coupled to the row and column driver, wherein each pixel circuit comprises at least two transistors in series connected to a pixel of a Liquid Crystal Display (LCD); wherein the row and column driver is configured to load a frame onto the LCD by applying positive voltages to the transistors of said transistors in series of the pixel circuits to form conduction paths to the pixels of the LCD and sending charges to the pixels through the conduction paths, and between frame load operations, for each pixel circuit, to alternately apply a negative gate bias voltage to one of the transistors of said transistors in series of the pixel circuit to hold the charge of the corresponding LCD pixel, and when the negative gate bias voltage is applied to a least one transistor of said transistors in series of the pixel circuit, a positive gate bias voltage is applied to the at least one other transistor of the pixel circuit, thereby applying a stress reducing voltage to the at least one other transistor of said transistors in series of the pixel circuit, wherein said negative gate bias voltage and positive gate bias voltage are alternately applied between frame loading operations to each one of said transistors in series.
A display circuit for an active matrix LCD includes a row and column driver and multiple pixel circuits. Each pixel circuit contains at least two transistors connected in series to a pixel. The row and column driver loads frames onto the LCD by applying positive voltages to the transistors in the pixel circuits, forming conductive paths to the LCD pixels, and then sending charge to the pixels. In between frame loading, the driver alternates the gate bias voltage to each of the transistors in series. When one transistor has a negative gate bias voltage, the other transistor has a positive gate bias voltage applied. This stress reducing voltage is alternately applied between the transistors in series.
9. The display circuit of claim 8 , wherein the row and column driver is configured to apply the negative gate bias voltage to one of the transistors of said transistors in series of the pixel circuit at a rate of 60 Hz or greater.
The display circuit described previously, where each pixel circuit includes at least two transistors in series and the gate bias voltage is alternated, specifies that the row and column driver alternates the negative gate bias voltage applied to each of the transistors in series at a rate of 60 Hz or greater.
10. The display circuit of claim 8 , wherein the row and column driver is configured to update the frame of the LCD at a rate of 200 milliseconds or slower.
The display circuit described previously, where each pixel circuit includes at least two transistors in series and the gate bias voltage is alternated, updates the frames of the LCD at a rate of 200 milliseconds or slower. This corresponds to a frame rate of 5 frames per second or slower.
11. The display circuit of claim 8 , wherein the row and column driver is configured to update the frame of the LCD at a rate of one second or slower.
The display circuit described previously, where each pixel circuit includes at least two transistors in series and the gate bias voltage is alternated, updates the frames of the LCD at a rate of one second or slower. This corresponds to a frame rate of 1 frame per second or slower.
12. The display circuit of claim 8 , wherein transistors comprise amorphous silicon hydrogenated thin film transistors (a-Si:H TFT).
The display circuit described previously, where each pixel circuit includes at least two transistors in series and the gate bias voltage is alternated, uses amorphous silicon hydrogenated thin film transistors (a-Si:H TFT) for the transistors in the pixel circuits.
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December 3, 2007
July 2, 2013
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