Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor integrated circuit device comprising: a first bit line extended along a first direction; a second bit line extended along the first direction; a word line extended along a second direction, the second direction being perpendicular to the first direction; a first P-type well extended along the first direction; a second P-type well extended along the first direction; an N-type well extended along the first direction, and provided between the first P-type well and the second P-type well; and a memory cell having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal of the second inverter being coupled to an output terminal of the first inverter and with an output terminal of the second inverter being coupled to an input terminal of the first inverter, a third N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the second inverter and the second bit line, a gate electrode of the third N-channel MOS transistor and a gate electrode of the fourth N-channel MOS transistor both being coupled to the word line; wherein the first N-channel MOS transistor and the third N-channel MOS transistor in the memory cell are located at the first P-type well, wherein the first P-channel MOS transistor and the second P-channel MOS transistor in the memory cell are located at the N-type well, wherein the second N-channel MOS transistor and the third N-channel MOS transistor in the memory cell are located at the second P-type well, wherein a first wiring layer includes a first portion serving as a gate electrode of the first N-channel MOS transistor and a second portion serving as a gate electrode of the first P-channel MOS transistor of the memory cell, wherein a second wiring layer includes a third portion serving as a gate electrode of the second N-channel MOS transistor and a fourth portion serving as a gate electrode of the second P-channel MOS transistor of the memory cell, wherein a third wiring layer includes a fifth portion serving as the gate electrode of the third N-channel MOS transistor of the memory cell, wherein a fourth wiring layer includes a sixth portion serving as the gate electrode of the fourth N-channel MOS transistor of the memory cell, and wherein an entirety of each of the first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer in plan view is substantially rectangular.
A semiconductor integrated circuit includes an SRAM memory cell with bit lines running in one direction and a word line perpendicular to them. The cell consists of two inverters (each with an N-channel and a P-channel transistor) connected in a loop, plus two N-channel transistors acting as access transistors to the bit lines, controlled by the word line. The first N-channel and the third N-channel transistors are in a first P-type well; the P-channel transistors are in an N-type well; and the second N-channel transistor and the fourth N-channel transistors are in a second P-type well. Gate electrodes of each transistor are formed by individual rectangular-shaped wiring layers.
2. The semiconductor integrated circuit device according to claim 1 , further comprising: a first contact connected to the third wiring layer and for coupling the third wiring layer to the word line; and a second contact connected to the fourth wiring layer and for coupling the fourth wiring layer to the word line, wherein a contact width of the first contact along the first direction is greater than a gate length of the third wiring layer along the first direction; and wherein a contact width of the second contact along the first direction is greater than a gate length of the fourth wiring layer along the first direction.
The SRAM cell from the previous description has contacts connecting the gate electrodes of the third and fourth N-channel access transistors to the word line. The contacts are wider than the gate length of those access transistors.
3. The semiconductor integrated circuit device according to claim 1 , wherein a first source area of the first N-channel MOS transistor is sandwiched by a field oxide, wherein a second source area of the second N-channel MOS transistor is sandwiched by the field oxide, wherein a pair of first edges of the first source area is extended along the first direction, the pair of first edges each being in direct contact with the field oxide, and wherein a pair of second edges of the second source area is extended along the first direction, the pair of second edges being in direct contact with the field oxide.
In the SRAM cell described earlier, the source areas of the first and second N-channel transistors are each surrounded by a field oxide isolation. The edges of these source areas run parallel to the bit lines and are directly adjacent to the field oxide.
4. The semiconductor integrated circuit device according to claim 2 , wherein a first source area of the first N-channel MOS transistor is sandwiched by a field oxide, wherein a second source area of the second N-channel MOS transistor is sandwiched by the field oxide, wherein a pair of first edges of the first source area is extended along the first direction, the pair of first edges are each being in direct contact with the field oxide, and wherein a pair of second edges of the second source area is extended along the first direction, the pair of second edges each being in direct contact with the field oxide.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are each surrounded by a field oxide isolation. The edges of these source areas run parallel to the bit lines and are directly adjacent to the field oxide.
5. The semiconductor integrated circuit device according to claim 1 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, and wherein the second source area has a pair of second edges extended along the first direction.
In the described SRAM cell, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines.
6. The semiconductor integrated circuit device according to claim 2 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, and wherein the second source area has a pair of second edges extended along the first direction.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines.
7. The semiconductor integrated circuit device according to claim 1 , wherein the first N-channel MOS transistor has a first source diffusion layer sandwiched by a field isolation, wherein the second N-channel MOS transistor has a second source diffusion layer sandwiched by the field isolation, wherein the first source diffusion layer includes a pair of first edges extended along the first direction, wherein the second source diffusion layer includes a pair of second edges extended along the first direction, wherein, in plan view, no p-type diffusion layer is in direct contact with the first edges in the memory cell, and wherein, in plan view, no p-type diffusion layer is in direct contact with the second edges in the memory cell.
In the described SRAM cell, the source diffusion layers of the first and second N-channel transistors are surrounded by field isolation. The edges of these source diffusion layers run parallel to the bit lines. No P-type diffusion areas directly touch these edges within the memory cell.
8. The semiconductor integrated circuit device according to claim 2 , wherein the first N-channel MOS transistor has a first source diffusion layer sandwiched by a field isolation, wherein the second N-channel MOS transistor has a second source area diffusion layer sandwiched by the field isolation, wherein the first source diffusion layer includes a pair of first edges extended along the first direction, wherein the second source diffusion layer includes a pair of second edges extended along the first direction, wherein, in plan view, no p-type diffusion layer is in direct contact with the first edges in the memory cell, and wherein, in plan view, no p-type diffusion layer is in direct contact with one of the second edges in the memory cell.
In the SRAM cell with wider contacts to the word line as described earlier, the source diffusion layers of the first and second N-channel transistors are surrounded by field isolation. The edges of these source diffusion layers run parallel to the bit lines. No P-type diffusion areas directly touch these edges within the memory cell.
9. The semiconductor integrated circuit device according to claim 1 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, wherein the second source area has a pair of second edges extended along the first direction, wherein the first P-type well is coupled to a first well contact outside of the memory cell, and wherein the second P-type well is coupled to a second well contact outside of the memory cell.
In the described SRAM cell, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines. The first and second P-type wells are connected to separate contacts located outside the memory cell, for supplying voltage.
10. The semiconductor integrated circuit device according to claim 2 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, wherein the second source area has a pair of second edges extended along the first direction, wherein the first P-type well is coupled to a first well contact outside of the memory cell, and wherein the second P-type well is coupled to a second well contact outside of the memory cell.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines. The first and second P-type wells are connected to separate contacts located outside the memory cell, for supplying voltage.
11. A semiconductor integrated circuit device comprising: a first bit line extended along a first direction; a second bit line extended along the first direction; a word line extended along a second direction, the second direction being perpendicular to the first direction; a first P-type well; a second P-type well; an N-type well provided between the first P-type well and the second P-type well; and a memory cell having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal of the second inverter being coupled to an output terminal of the first inverter and with an output terminal of the second inverter being coupled to an input terminal of the first inverter, a third N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the second inverter and the second bit line, a gate electrode of the third N channel MOS transistor and a gate electrode of the fourth N-channel MOS transistor both being coupled to the word line; wherein the first N channel MOS transistor and the third N-channel MOS transistor in the memory cell are located at the first P-type well, wherein the first P-channel MOS transistor and the second P-channel MOS transistor in the memory cell are located at the N-type well, wherein the second N-channel MOS transistor and the fourth N-channel MOS transistor in the memory cell are located at the second P-type well, wherein a first wiring layer includes a first portion serving as a gate electrode of the first N-channel MOS transistor and a second portion serving as a gate electrode of the first P-channel MOS transistor of the memory cell, wherein a second wiring layer includes a third portion serving as a gate electrode of the second N-channel MOS transistor and a fourth portion serving as a gate electrode of the second P-channel MOS transistor of the memory cell, wherein a third wiring layer includes a fifth portion serving as the gate electrode of the third N-channel MOS transistor of the memory cell, wherein a fourth wiring layer includes a sixth portion serving as the gate electrode of the fourth N-channel MOS transistor of the memory cell, and wherein an entity of each of the first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer in plan view is substantially rectangular.
A semiconductor integrated circuit includes an SRAM memory cell with bit lines running in one direction and a word line perpendicular to them. The cell consists of two inverters (each with an N-channel and a P-channel transistor) connected in a loop, plus two N-channel transistors acting as access transistors to the bit lines, controlled by the word line. The first N-channel and the third N-channel transistors are in a first P-type well; the P-channel transistors are in an N-type well; and the second N-channel transistor and the fourth N-channel transistors are in a second P-type well. Gate electrodes of each transistor are formed by individual rectangular-shaped wiring layers.
12. The semiconductor integrated circuit device according to claim 11 , further comprising: a first contact for connecting the third wiring layer with the word line; and a second contact for connecting the fourth wiring layer with the word line, wherein a contact width of the first contact along the first direction is larger than a gate length of the third wiring layer along the first direction; and wherein a contact width of the second contact along the first direction is larger than a gate length of the fourth wiring layer along the first direction.
The SRAM cell from the previous description has contacts connecting the gate electrodes of the third and fourth N-channel access transistors to the word line. The contacts are wider than the gate length of those access transistors.
13. The semiconductor integrated circuit device according to claim 11 , wherein a first source area of the first N-channel MOS transistor is sandwiched by a field oxide, wherein a second source area of the second N-channel MOS transistor is sandwiched by the field oxide, wherein a pair of first edges of the first source area is extended along the first direction, the pair of first edges each being in direct contact with the field oxide, and wherein a pair of second edges of the second source area is extended along the first direction, the pair of second edges each being in direct contact with the field oxide.
In the SRAM cell described earlier, the source areas of the first and second N-channel transistors are each surrounded by a field oxide isolation. The edges of these source areas run parallel to the bit lines and are directly adjacent to the field oxide.
14. The semiconductor integrated circuit device according to claim 12 , wherein a first source area of the first N-channel MOS transistor is sandwiched by a field oxide, wherein a second source area of the second N-channel MOS transistor is sandwiched by the field oxide, wherein a pair of first edges of the first source area is extended along the first direction, the pair of first edges each being in direct contact with the field oxide, and wherein a pair of second edges of the second source area is extended along the first direction, the pair of second edges each being in direct contact with the field oxide.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are each surrounded by a field oxide isolation. The edges of these source areas run parallel to the bit lines and are directly adjacent to the field oxide.
15. The semiconductor integrated circuit device according to claim 11 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, and wherein the second source area has a pair of second edges extended along the first direction.
This invention relates to semiconductor integrated circuit devices, specifically addressing layout and structural improvements for N-channel MOS transistors to enhance performance and reliability. The device includes at least two N-channel MOS transistors, each with a source area surrounded by field oxide to isolate the transistor regions. The first N-channel MOS transistor has a first source area with edges extending along a first direction, while the second N-channel MOS transistor has a second source area with edges also extending along the same direction. The field oxide surrounds both source areas, ensuring electrical isolation and reducing leakage currents. The alignment of the source area edges along the same direction optimizes the transistor layout, improving manufacturing consistency and electrical characteristics. This configuration helps minimize parasitic effects, such as capacitance and resistance, while maintaining structural integrity. The invention is particularly useful in high-density integrated circuits where precise transistor placement and isolation are critical for performance and reliability. The field oxide surrounding the source areas prevents unwanted electrical interference, ensuring stable operation under varying conditions. The described structure is applicable in various semiconductor processes, including CMOS technology, to enhance device efficiency and scalability.
16. The semiconductor integrated circuit device according to claim 12 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, and wherein the second source area has a pair of second edges extended along the first direction.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines.
17. The semiconductor integrated circuit device according to claim 11 , wherein the first N-channel MOS transistor has a first source diffusion layer sandwiched by a field isolation, wherein the second N-channel MOS transistor has a second source diffusion layer sandwiched by the field isolation, wherein the first source diffusion layer includes a pair of first edges extended along the first direction, wherein the second source diffusion layer includes a pair of second edges extended along the first direction, wherein, in plane view, no p-type diffusion layer is in direct contact with the first edges in the memory cell, and wherein, in plan view, no p-type diffusion layer is in direct contact with the second edges in the memory cell.
In the described SRAM cell, the source diffusion layers of the first and second N-channel transistors are surrounded by field isolation. The edges of these source diffusion layers run parallel to the bit lines. No P-type diffusion areas directly touch these edges within the memory cell.
18. The semiconductor integrated circuit device according to claim 12 , wherein the first N-channel MOS transistor has a first source diffusion layer sandwiched by a field isolation, wherein the second N-channel MOS transistor has a second source diffusion layer sandwiched by the field isolation, wherein the first source diffusion layer includes a pair of first edges extended along the first direction, wherein the second source diffusion layer includes a pair of second edges extended along the first direction, wherein, in plane view, no p-type diffusion layer is in direct contact with the first edges in the memory cell, and wherein, in plan view, no p-type diffusion layer is in direct contact with the second edges in the memory cell.
In the SRAM cell with wider contacts to the word line as described earlier, the source diffusion layers of the first and second N-channel transistors are surrounded by field isolation. The edges of these source diffusion layers run parallel to the bit lines. No P-type diffusion areas directly touch these edges within the memory cell.
19. The semiconductor integrated circuit device according to claim 11 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, wherein the second source area has a pair of second edges extended along the first direction, wherein the first P-type well is coupled to a first well contact outside of the memory cell, and wherein the second P-type well is coupled to a second well contact outside of the memory cell.
In the described SRAM cell, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines. The first and second P-type wells are connected to separate contacts located outside the memory cell, for supplying voltage.
20. The semiconductor integrated circuit device according to claim 12 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, wherein the second source area has a pair of second edges extended along the first direction, wherein the first P-type well is coupled to a first well contact outside of the memory cell, and wherein the second P-type well is coupled to a second well contact outside of the memory cell.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines. The first and second P-type wells are connected to separate contacts located outside the memory cell, for supplying voltage.
21. A semiconductor integrated circuit device comprising: a first bit line extended along a first direction; a second bit line extended along the first direction; a word line extended along a second direction, the second direction crossing with the first direction; and a memory cell having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal of the second inverter being coupled to an output terminal of the first inverter and with an output terminal of the second inverter being coupled to an input terminal of the first inverter, a third N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the second inverter and the second bit line, a gate electrode of the third N-channel MOS transistor and a gate electrode of the fourth N-channel MOS transistor both being coupled to the word line; wherein the memory cell has a first part, second part and third part and the second part is located between the first part and third part, wherein the first N-channel MOS transistor and the third N-channel transistor in the memory cell are located at the first part, wherein the first P-channel MOS transistor and the second P-channel MOS transistor in the memory cell are located at the second part, wherein the second N channel MOS transistor and the third N-channel transistor in the memory cell are located at the third part, wherein a first gate wiring includes a first portion serving as a gate electrode of the first N-channel MOS transistor and a second portion serving as a gate electrode of the first P-channel MOS transistor of the memory cell, wherein a second gate wiring includes a third portion serving as a gate electrode of the second N-channel MOS transistor and a fourth portion serving as a gate electrode of the second P-channel MOS transistor of the memory cell, wherein a third gate wiring includes a fifth portion serving as the gate electrode of the third N-channel MOS transistor of the memory cell, wherein a fourth gate wiring includes a sixth portion serving as the gate electrode of the fourth N-channel MOS transistor of the memory cell, and wherein an entirety of each of the first gate wiring, the second gate wiring, the third gate wiring and the fourth gate wiring in plan view is substantially rectangular.
A semiconductor integrated circuit consists of an SRAM memory cell featuring bit lines running in one direction, and a word line crossing this direction. The cell consists of two inverters (each with an N-channel and a P-channel transistor) connected in a loop, plus two N-channel transistors serving as access transistors to the bit lines, these are controlled by the word line. The cell is divided into three sections: first, second and third part, where the second is between the first and third. The first N-channel transistor and the third N-channel transistor are located in the first section, the P-channel transistors in the second section, and the second N-channel and fourth N-channel in the third section. Each transistor's gate is controlled by individual rectangular wiring layers.
22. The semiconductor integrated circuit device according to claim 21 , further comprising: a first contact coupling the third gate wiring to the word line; and a second contact coupling the fourth gate wiring to the word line, wherein a contact width of the first contact along the first direction is larger than a gate length of the third gate wiring along the first direction; and wherein a contact width of the second contact along the first direction is larger than a gate length of the fourth gate wiring along the first direction.
The SRAM cell from the previous description has contacts connecting the gate electrodes of the third and fourth N-channel access transistors to the word line. The contacts are wider than the gate length of those access transistors.
23. The semiconductor integrated circuit device according to claim 21 , wherein a first source area of the first N-channel MOS transistor is surrounded by a field oxide, wherein a second source area of the second N-channel MOS transistor is surrounded by the field oxide, wherein a pair of first edges of the first source area is extended along the first direction, the pair of first edges each being in direct contact with the field oxide, and wherein a pair of second edges of the second source area is extended along the first direction, the paid of second edges each being in direct contact with the field oxide.
In the SRAM cell described earlier, the source areas of the first and second N-channel transistors are each surrounded by a field oxide isolation. The edges of these source areas run parallel to the bit lines and are directly adjacent to the field oxide.
24. The semiconductor integrated circuit device according to claim 22 , wherein a first source area of the first N-channel MOS transistor is surrounded by a field oxide, wherein a second source area of the second N-channel MOS transistor is surrounded by the field oxide, wherein a pair of first edges of the first source area is extended along the first direction, the pair of first edges each being in direct contact with the field oxide, and wherein a pair of second edges of the second source area is extended along the first direction, the pair of second edges each being in direct contact with the field oxide.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are each surrounded by a field oxide isolation. The edges of these source areas run parallel to the bit lines and are directly adjacent to the field oxide.
25. The semiconductor integrated circuit device according to claim 21 , wherein the first N-channel MOS transistor has a first source area surrounded by a field oxide, wherein the second N-channel MOS transistor has a second source area surrounded by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, and wherein the second source area has a pair of second edges extended along the first direction.
In the described SRAM cell, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines.
26. The semiconductor integrated circuit device according to claim 22 , wherein the first N-channel MOS transistor has a first source area surrounded by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, and wherein the second source area has a pair of second edges extended along the first direction.
In the SRAM cell with wider contacts to the word line as described earlier, the source area of the first N-channel transistor is surrounded by field oxide and the source area of the second N-channel transistor is sandwiched by field oxide. The edges of these source areas run parallel to the bit lines.
27. The semiconductor integrated circuit device according to claim 21 , wherein the first N-channel MOS transistor has a first source diffusion layer surrounded by a field isolation, wherein the second N-channel MOS transistor has a second source diffusion layer surrounded by the field isolation, wherein the first source diffusion layer includes a pair of first edges extended along the first direction, wherein the second source diffusion layer includes a pair of second edges extended along the first direction, wherein, in plan view, no p-type diffusion layer is in direct contact with the first edges in the memory cell, and wherein, in plan view, no p-type diffusion layer is in direct contact with one of the second edges in the memory cell.
In the described SRAM cell, the source diffusion layers of the first and second N-channel transistors are surrounded by field isolation. The edges of these source diffusion layers run parallel to the bit lines. No P-type diffusion areas directly touch these edges within the memory cell.
28. The semiconductor integrated circuit device according to claim 22 , wherein the first N-channel MOS transistor has a first source diffusion layer surrounded by a field isolation, wherein the second N-channel MOS transistor has a second source diffusion layer surrounded by the field isolation, wherein the first source diffusion layer includes a pair of first edges extended along the first direction, wherein the second source diffusion layer includes a pair of second edges extended along the first direction, wherein, in plan view, no p-type diffusion layer is in direct contact with the first edges in the memory cell, and wherein, in plan view, no p-type diffusion layer is in direct contact with the second edges in the memory cell.
In the SRAM cell with wider contacts to the word line as described earlier, the source diffusion layers of the first and second N-channel transistors are surrounded by field isolation. The edges of these source diffusion layers run parallel to the bit lines. No P-type diffusion areas directly touch these edges within the memory cell.
29. The semiconductor integrated circuit device according to claim 21 , wherein the first N-channel MOS transistor has a first source area surrounded by a field oxide, wherein the second N-channel MOS transistor has a second source area surrounded by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, wherein the second source area has a pair of second edges extended along the first direction, wherein the first part is coupled to a first contact for supplying a voltage to the first part outside of the memory cell, and wherein the second part is coupled to a second contact for supplying the voltage to the second part outside of the memory cell.
In the described SRAM cell, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines. The first and second part are connected to separate contacts located outside the memory cell, for supplying voltage.
30. The semiconductor integrated circuit device according to claim 22 , wherein the first N-channel MOS transistor has a first source area surrounded by a field oxide, wherein the second N-channel MOS transistor has a second source area surrounded by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, wherein the second source area has a pair of second edges extended along the first direction, wherein the first part is coupled to a first contact for supplying a voltage to the first part outside of the memory cell, and wherein the second part is coupled to a second contact for supplying the voltage to the second part outside of the memory cell.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines. The first and second part are connected to separate contacts located outside the memory cell, for supplying voltage.
31. A semiconductor integrated circuit device comprising: a first bit line extended along a first direction; a second bit line extended along the first direction; a word line extended along a second direction, the second direction being perpendicular to the first direction; a first P-type well extended along the first direction; a second P-type well extended along the first direction; an N-type well extended along the first direction, and provided between the first P-type well and the second P-type well; and a memory cell having a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal of the second inverter being coupled to an output terminal of the first inverter and with an output terminal of the second inverter being coupled to an input terminal of the first inverter, a third N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the first inverter and the first bit line, and a fourth N-channel MOS transistor having a source/drain path thereof coupled between the output terminal of the second inverter and the second bit line, a gate electrode of the third N channel MOS transistor and a gate electrode of the fourth N-channel MOS transistor both being coupled to the word line; wherein the first N-channel MOS transistor and the third N-channel MOS transistor in the memory cell are located at the first P-type well, wherein the first P-channel MOS transistor and the second P-channel MOS transistor in the memory cell are located at the N-type well, wherein the second N channel MOS transistor and the third N-channel MOS transistor in the memory cell are located at the second P-type well, wherein a first wiring layer includes a first portion serving as a gate electrode of the first N-channel MOS transistor and a second portion serving as a gate electrode of the first P-channel MOS transistor of the memory cell, wherein a second wiring layer includes a third portion serving as a gate electrode of the second N-channel MOS transistor and a fourth portion serving as a gate electrode of the second P-channel MOS transistor of the memory cell, wherein a third wiring layer includes a fifth portion serving as the gate electrode of the third N-channel MOS transistor of the memory cell, wherein a fourth wiring layer includes a sixth portion serving as the gate electrode of the fourth N-channel MOS transistor of the memory cell, and wherein an entirety of each of the first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer in plan view has a substantially uniform gate length, measured along the first direction.
A semiconductor integrated circuit includes an SRAM memory cell with bit lines running in one direction and a word line perpendicular to them. The cell consists of two inverters (each with an N-channel and a P-channel transistor) connected in a loop, plus two N-channel transistors acting as access transistors to the bit lines, controlled by the word line. The first N-channel and the third N-channel transistors are in a first P-type well; the P-channel transistors are in an N-type well; and the second N-channel transistor and the fourth N-channel transistors are in a second P-type well. Gate electrodes of each transistor are formed by individual wiring layers having a substantially uniform gate length when viewed from above.
32. The semiconductor integrated circuit device according to claim 31 , further comprising: a first contact connected to the third wiring layer and for coupling the third wiring layer to the word line; and a second contact connected to the fourth wiring layer and for coupling the fourth wiring layer to the word line, wherein a contact width of the first contact along the first direction is greater than a gate length of the third wiring layer along the first direction; and wherein a contact width of the second contact along the first direction is greater than a gate length of the fourth wiring layer along the first direction.
The SRAM cell from the previous description has contacts connecting the gate electrodes of the third and fourth N-channel access transistors to the word line. The contacts are wider than the gate length of those access transistors.
33. The semiconductor integrated circuit device according to claim 31 , wherein a first source area of the first N-channel MOS transistor is sandwiched by a field oxide, wherein a second source area of the second N-channel MOS transistor is sandwiched by the field oxide, wherein a pair of first edges of the first source area is extended along the first direction, the pair of first edges each being in direct contact with the field oxide, and wherein a pair of second edges of the second source area is extended along the first direction, the pair of second edges each being in direct contact with the field oxide.
In the SRAM cell described earlier, the source areas of the first and second N-channel transistors are each surrounded by a field oxide isolation. The edges of these source areas run parallel to the bit lines and are directly adjacent to the field oxide.
34. The semiconductor integrated circuit device according to claim 32 , wherein a first source area of the first N-channel MOS transistor is sandwiched by a field oxide, wherein a second source area of the second N-channel MOS transistor is sandwiched by the field oxide, wherein a pair of first edges of the first source area is extended along the first direction, the pair of first edges each being in direct contact with the field oxide, and wherein a pair of second edges of the second source area is extended along the first direction, the pair of second edges each being in direct contact with the field oxide.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are each surrounded by a field oxide isolation. The edges of these source areas run parallel to the bit lines and are directly adjacent to the field oxide.
35. The semiconductor integrated circuit device according to claim 31 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, and wherein the second source area has a pair of second edges extended along the first direction.
In the described SRAM cell, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines.
36. The semiconductor integrated circuit device according to claim 32 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, and wherein the second source area has a pair of second edges extended along the first direction.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines.
37. The semiconductor integrated circuit device according to claim 31 , wherein the first N-channel MOS transistor has a first source diffusion layer sandwiched by a field isolation, wherein the second N-channel MOS transistor has a second source diffusion layer sandwiched by the field isolation, wherein the first source diffusion layer includes a pair of first edges extended along the first direction, wherein the second source diffusion layer includes a pair of second edges extended along the first direction, wherein, in plan view, no p-type diffusion layer is in direct contact with the first edges in the memory cell, and wherein, in plan view, no p-type diffusion layer is in direct contact with the second edges in the memory cell.
In the described SRAM cell, the source diffusion layers of the first and second N-channel transistors are surrounded by field isolation. The edges of these source diffusion layers run parallel to the bit lines. No P-type diffusion areas directly touch these edges within the memory cell.
38. The semiconductor integrated circuit device according to claim 32 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field isolation, wherein the second N-channel MOS transistor has a second source area sandwiched by the field isolation, wherein the first source diffusion layer includes a pair of first edges extended along the first direction, wherein the second source diffusion layer includes a pair of second edges extended along the first direction, wherein, in plan view, no p-type diffusion layer is in direct contact with the first edges in the memory cell, and wherein, in plan view, no p-type diffusion layer is in direct contact with the second edges in the memory cell.
In the SRAM cell with wider contacts to the word line as described earlier, the source diffusion layers of the first and second N-channel transistors are surrounded by field isolation. The edges of these source diffusion layers run parallel to the bit lines. No P-type diffusion areas directly touch these edges within the memory cell.
39. The semiconductor integrated circuit device according to claim 31 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, wherein the second source area has a pair of second edges extended along the first direction, wherein the first P-type well is coupled to a first well contact outside of the memory cell, and wherein the second P-type well is coupled to a second well contact outside of the memory cell.
In the described SRAM cell, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines. The first and second P-type wells are connected to separate contacts located outside the memory cell, for supplying voltage.
40. The semiconductor integrated circuit device according to claim 32 , wherein the first N-channel MOS transistor has a first source area sandwiched by a field oxide, wherein the second N-channel MOS transistor has a second source area sandwiched by the field oxide, wherein the first source area has a pair of first edges extended along the first direction, wherein the second source area has a pair of second edges extended along the first direction, wherein the first P-type well is coupled to a first well contact outside of the memory cell, and wherein the second P-type well is coupled to a second well contact outside of the memory cell.
In the SRAM cell with wider contacts to the word line as described earlier, the source areas of the first and second N-channel transistors are surrounded by a field oxide. The edges of these source areas run parallel to the bit lines. The first and second P-type wells are connected to separate contacts located outside the memory cell, for supplying voltage.
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June 23, 2010
July 9, 2013
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