An electronic component incorporation substrate and a method for manufacturing the same that provide a high degree of freedom for selecting materials. An electronic component incorporation substrate includes a first structure, which has a substrate and an electronic component. The substrate includes a substrate body having first and second surfaces. A first wiring pattern is formed on the first surface and electrically connected to a second wiring pattern formed on the second surface through a through via. The electronic component is electrically connected to the first wiring pattern. The electronic component incorporation substrate includes a sealing resin, which seals the first structure, and a third wiring pattern, which is connected to the second wiring pattern through a second via.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a first structure including a first substrate and an electronic component, wherein the first substrate includes a first surface and an opposite second surface, and the electronic component is arranged on the first surface of the first substrate and electrically connected to first wiring pattern formed on the first surface of the first substrate by solder; a first sealing resin layer that seals the first structure and is formed on the first surface of the first substrate; a second sealing resin layer that further seals and completely covers the first structure, wherein the second sealing resin layer includes a first surface and a second surface opposite the first surface; an insulation layer formed on the second surface of the first substrate and the first surface of the second sealing resin layer, wherein the insulation layer is larger than the first substrate when viewed from above; a via that extends through the insulation layer and is directly connected to a second wiring pattern formed on the second surface of the first substrate; additional wiring formed on the insulation layer and electrically connected to the electronic component through the first substrate and the via; another insulation layer formed on the second surface of the second sealing resin layer; and further wiring formed on another insulation later.
2. The semiconductor device according to claim 1 , further comprising a second substrate that is sealed by the second sealing resin layer, wherein the second substrate includes a first surface and an opposite second surface, and the first and second surfaces of the second substrate are electrically connected, wherein the first and second surfaces of the second sealing resin layer are electrically connected through the second substrate.
3. The semiconductor device according to claim 1 , wherein and the second sealing resin layer further includes a through electrode that extends through the second sealing resin layer and electrically connects the first and second surfaces of the second sealing resin layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 13, 2011
July 9, 2013
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